參數(shù)資料
型號(hào)： EPM7128ABC100-6
廠商： ALTERA CORP
元件分類： PLD
英文描述： EE PLD, 6 ns, PBGA100
文件頁(yè)數(shù)： 31/51頁(yè)
文件大?。?/td> 1559K
代理商： EPM7128ABC100-6
Altera Corporation
631
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Notes to tables:
(1)
These values are specified in Table 10 on page 616.
(2)
These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(3)
Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(4)
The fMAX values represent the highest frequency for pipelined data.
(5)
Operating conditions: VCCIO = 2.5 ± 0.2 V for commercial and industrial use.
(6)
The tLPA parameter must be added to the tLAD, tLAC, tIC, tACL, tEN, and tSEXP parameters for macrocells running in
low-power mode.
(7)
MAX 7000AE timing values are preliminary.
Power
Consumption
Supply power (P) versus frequency (fMAX, in MHz) for MAX 7000A
devices is calculated with the following equation:
P = PINT + PIO = ICCINT × VCC + PIO
The PIO value, which depends on the device output load characteristics
and switching frequency, can be calculated using the guidelines given in
The ICCINT value depends on the switching frequency and the application
logic. The ICCINT value is calculated with the following equation:
ICCINT =
(A
× MC
TON) + [B × (MCDEV – MCTON)] + (C × MCUSED × fMAX × togLC)
The parameters in this equation are:
MCTON
= Number of macrocells with the Turbo BitTM option turned
on, as reported in the MAX+PLUS II Report File (.rpt)
MCDEV
= Number of macrocells in the device
MCUSED = Total number of macrocells in the design, as reported in
the Report File
fMAX
= Highest clock frequency to the device
togLC
= Average percentage of logic cells toggling at each clock
(typically 12.5%)
A, B, C
= Constants, shown in Table 21
相關(guān)PDF資料
PDF描述
EPM7128ABC100-7 EE PLD, 7.5 ns, PBGA100
EPM7128ABI100-10 EE PLD, 10 ns, PBGA100
EPM7128ABI100-12 EE PLD, 12 ns, PBGA100
EPM7128ABI100-6 EE PLD, 6 ns, PBGA100
EPM7128ABI100-7 EE PLD, 7.5 ns, PBGA100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM7128AE 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device
EPM7128AEFC100-10 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7128AEFC100-10N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7128AEFC100-5 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7128AEFC100-5N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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