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參數(shù)資料
| 型號： | EPM3128A |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family |
| 中文描述： | 可編程邏輯器件系列 |
| 文件頁數(shù)： | 13/42頁 |
| 文件大?。?/td> | 649K |
| 代理商： | EPM3128A |
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Altera Corporation
13
MAX 3000A Programmable Logic Device Family Data Sheet
The Altera software can use text– or waveform–format test vectors created
with the Altera Text Editor or Waveform Editor to test the programmed
device. For added design verification, designers can perform functional
testing to compare the functional device behavior with the results of
simulation.
Data I/ O, BP Microsystems, and other programming hardware
manufacturers also provide programming support for Altera devices.
f
For more information, see
Programming Hardware Manufacturers
.
IEEE Std.
1149.1 (JTAG)
Boundary–Scan
Support
MAX 3000A devices include the JTAG BST circuitry defined by IEEE
Std. 1149.1–1990.
Table 4
describes the JTAG instructions supported by
MAX 3000A devices. The pin-out tables found on the Altera web site
(
http://www.altera.com
) or the
Altera Digital Library
show the location of
the JTAG control pins for each device. If the JTAG interface is not
required, the JTAG pins are available as user I/ O pins.
The instruction register length of MAX 3000A devices is 10 bits. The
IDCODE and USERCODE register length is 32 bits.
Tables 5
and
6
show
the boundary–scan register length and device IDCODE information for
MAX 3000A devices.
Table 4. MAX 3000A JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern output at the device pins
Allows the external circuitry and board–level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins
Places the 1–bit bypass register between the
TDI
and
TDO
pins, which allows the BST
data to pass synchronously through a selected device to adjacent devices during normal
device operation
Selects the IDCODE register and places it between the
TDI
and
TDO
pins, allowing the
IDCODE to be serially shifted out of
TDO
Selects the 32–bit USERCODE register and places it between the
TDI
and
TDO
pins,
allowing the USERCODE value to be shifted out of
TDO
These instructions are used when programming MAX 3000A devices via the JTAG ports
with the MasterBlaster, ByteBlasterMV, or BitBlaster cable, or when using a Jam STAPL
file, JBC file, or SVF file via an embedded processor or test equipment
EXTEST
BYPASS
IDCODE
USERCODE
ISP Instructions
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPM3128AFC256-10 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Altera Corporation 功能描述:IC CPLD 128MC 10NS 256FBGA 制造商:Altera Corporation 功能描述:IC MAX 256FBGA |
| EPM3128AFC256-5 | 制造商:Altera Corporation 功能描述:IC MAX 256FBGA 制造商:Altera Corporation 功能描述:IC CPLD 128MC 7.5NS 256FBGA |
| EPM3128AFC256-7 | 制造商:Altera Corporation 功能描述:IC MAX |
| EPM3128AFC256-7N | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 3000A 128 Macro 98 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM3128AFI256-10 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 3000A 128 Macro 98 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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