參數(shù)資料
型號： EPM2210GF324A4N
廠商： ALTERA CORP
元件分類： PLD
英文描述： FLASH PLD, PBGA324
封裝： 19 X 19 MM, 1 MM PITCH, LEAD FREE, FBGA-324
文件頁數(shù)： 62/108頁
文件大?。?/td> 1342K
代理商： EPM2210GF324A4N
Altera Corporation
Core Version a.b.c variable
3–7
December 2007
MAX II Device Handbook, Volume 1
JTAG and In-System Programmability
2.
Check ID—Before any program or verify process, the silicon ID is
checked. The time required to read this silicon ID is relatively small
compared to the overall programming time.
3.
Sector Erase—Erasing the device in-system involves shifting in the
instruction to erase the device and applying an erase pulse(s). The
erase pulse is automatically generated internally by waiting in the
run/test/idle state for the specified erase pulse time of 500 ms for
the CFM block and 500 ms for each sector of the UFM block.
4.
Program—Programming the device in-system involves shifting in
the address, data, and program instruction and generating the
program pulse to program the flash cells. The program pulse is
automatically generated internally by waiting in the run/test/idle
state for the specified program pulse time of 75 s. This process is
repeated for each address in the CFM and UFM blocks.
5.
Verify—Verifying a MAX II device in-system involves shifting in
addresses, applying the verify instruction to generate the read
pulse, and shifting out the data for comparison. This process is
repeated for each CFM and UFM address.
6.
Exit ISP—An exit ISP stage ensures that the I/O pins transition
smoothly from ISP mode to user mode.
Table 3–4 shows the programming times for MAX II devices using
in-circuit testers to execute the algorithm vectors in hardware.
Software-based programming tools used with download cables are
slightly slower because of data processing and transfer limitations.
Table 3–4. MAX II Device Family Programming Times
Description
EPM240
EPM240G
EPM240Z
EPM570
EPM570G
EPM570Z
EPM1270
EPM1270G
EPM2210
EPM2210G
Unit
Erase + Program (1 MHz)
1.72
2.16
2.90
3.92
sec
Erase + Program (10 MHz)
1.65
1.99
2.58
3.40
sec
Verify (1 MHz)
0.09
0.17
0.30
0.49
sec
Verify (10 MHz)
0.01
0.02
0.03
0.05
sec
Complete Program Cycle (1 MHz)
1.81
2.33
3.20
4.41
sec
Complete Program Cycle (10 MHz)
1.66
2.01
2.61
3.45
sec
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM2210GF324C3 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 272 IO RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM2210GF324C3N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 272 IO RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM2210GF324C4 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 272 IO RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM2210GF324C4N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 272 IO RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM2210GF324C5 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 272 IO RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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