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參數(shù)資料
| 型號： | EPM2210GF324A4N |
| 廠商： | ALTERA CORP |
| 元件分類： | PLD |
| 英文描述： | FLASH PLD, PBGA324 |
| 封裝： | 19 X 19 MM, 1 MM PITCH, LEAD FREE, FBGA-324 |
| 文件頁數(shù)： | 25/108頁 |
| 文件大?。?/td> | 1342K |
| 代理商： | EPM2210GF324A4N |
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Altera Corporation
2–15
March 2008
MAX II Device Handbook, Volume 1
MAX II Architecture
Clear and Preset Logic Control
LAB-wide signals control the logic for the register’s clear and preset
signals. The LE directly supports an asynchronous clear and preset
function. The register preset is achieved through the asynchronous load
of a logic high. MAX II devices support simultaneous
preset/asynchronous load and clear signals. An asynchronous clear
signal takes precedence if both signals are asserted simultaneously. Each
LAB supports up to two clears and one preset signal.
In addition to the clear and preset ports, MAX II devices provide a
chip-wide reset pin (DEV_CLRn) that resets all registers in the device. An
option set before compilation in the Quartus II software controls this pin.
This chip-wide reset overrides all other control signals and uses its own
dedicated routing resources (that is, it does not use any of the four global
resources). Driving this signal low before or during power-up prevents
user mode from releasing clears within the design. This allows you to
control when clear is released on a device that has just been powered-up.
If not set for its chip-wide reset function, the DEV_CLRn pin is a regular
I/O pin.
By default, all registers in MAX II devices are set to power-up low.
However, this power-up state can be set to high on individual registers
during design entry using the Quartus II software.
MultiTrack
Interconnect
In the MAX II architecture, connections between LEs, the UFM, and
device I/O pins are provided by the MultiTrack interconnect structure.
The MultiTrack interconnect consists of continuous,
performance-optimized routing lines used for inter- and intra-design
block connectivity. The Quartus II Compiler automatically places critical
design paths on faster interconnects to improve design performance.
The MultiTrack interconnect consists of row and column interconnects
that span fixed distances. A routing structure with fixed length resources
for all devices allows predictable and short delays between logic levels
instead of large delays associated with global or long routing lines.
Dedicated row interconnects route signals to and from LABs within the
same row. These row resources include:
■
DirectLink interconnects between LABs
■
R4 interconnects traversing four LABs to the right or left
The DirectLink interconnect allows an LAB to drive into the local
interconnect of its left and right neighbors. The DirectLink interconnect
provides fast communication between adjacent LABs and/or blocks
without using row interconnect resources.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPM2210GF324C3 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 272 IO RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM2210GF324C3N | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 272 IO RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM2210GF324C4 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 272 IO RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM2210GF324C4N | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 272 IO RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM2210GF324C5 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 272 IO RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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