參數(shù)資料
型號(hào)： EPC4xxx
廠商： Altera Corporation
英文描述： 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
中文描述： 2。增強(qiáng)型配置器件（EPC4，EPC8
文件頁(yè)數(shù)： 25/36頁(yè)
文件大小： 421K
代理商： EPC4XXX
Altera Corporation
August 2005
2–25
Configuration Handbook, Volume 2
Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
The enhanced configuration device supports a programmable POR delay
setting. You can set the POR delay to the default 100-ms setting or reduce
the POR delay to 2 ms for systems that require fast power-up. The
PORSEL
input pin controls this POR delay; a logic high level selects the
2-ms delay, while a logic low level selects the 100-ms delay.
The enhanced configuration device can enter reset under the following
conditions:
■
The POR reset starts at initial power-up during V
CC
ramp-up or if
V
CC
drops below the minimum operating condition anytime after
V
CC
has stabilized
The FPGA initiates reconfiguration by driving
nSTATUS
low, which
occurs if the FPGA detects a CRC error or if the FPGA’s
nCONFIG
input pin is asserted
The controller detects a configuration error and asserts
OE
to initiate
re-configuration of the Altera FPGA (for example when
CONF_DONE
stays low after all configuration data has been transmitted)
■
■
Power
Sequencing
Altera requires that you power-up the FPGA's V
CCINT
supply before the
enhanced configuration device's POR expires.
Power up needs to be controlled so that the enhanced configuration
device’s
OE
signal goes high after the
CONF_DONE
signal is pulled low. If
the EEPC device exits POR before the FPGA is powered up, the
CONF_DONE
signal will be high since the pull-up resistor is holding this
signal high. When the enhanced configuration device exits POR,
OE
is
released and pulled high by a pull-up resistor. Since the enhanced
configuration device samples the
nCS
signal on the rising edge of
OE
, it
detects a high level on
CONF_DONE
and enters an idle mode.
DATA
and
DCLK
outputs will not toggle in this state and configuration will not
begin. The enhanced configuration device will only exit this mode if it is
powered down and then powered up correctly.
1
To ensure the enhanced configuration device enters
configuration mode properly, you need to ensure that the FPGA
completes power-up before the enhanced configuration device
exits POR.
The pin-selectable POR time feature is useful for ensuring this power-up
sequence. The enhanced configuration device has two POR settings, 2 ms
when
PORSEL
is set to a high level and 100 ms when
PORSEL
is set to a
low level. For more margin, the 100-ms setting can be selected to allow the
FPGA to power-up before configuration is attempted.
相關(guān)PDF資料
PDF描述
EPC16QC100 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC16QI100 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC8xxx 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC8QC100 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC8QI100 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPC50C605 制造商:Rochester Electronics LLC 功能描述:- Bulk
EPC-525-0.5 制造商:EPIGAP 制造商全稱:EPIGAP 功能描述:Photodiode-Chip
EPC-525-0.5-2 制造商:EPIGAP 制造商全稱:EPIGAP 功能描述:Photodiode-Chip
EPC-525-0.9-1 制造商:EPIGAP 制造商全稱:EPIGAP 功能描述:Photodiode-Chip
EPC-525-1.4 制造商:EPIGAP 制造商全稱:EPIGAP 功能描述:Photodiode-Chip
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*