參數(shù)資料
型號: EPC4xxx
廠商: Altera Corporation
英文描述: 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
中文描述: 2。增強(qiáng)型配置器件(EPC4,EPC8
文件頁數(shù): 18/36頁
文件大?。?/td> 421K
代理商: EPC4XXX
2–18
Configuration Handbook, Volume 2
Altera Corporation
August 2005
Functional Description
Programmable Configuration Clock
The configuration clock (
DCLK
) speed is user programmable. One of two
clock sources can be used to synthesize the configuration clock; a
programmable oscillator or an external clock input pin (
EXCLK
). The
configuration clock frequency can be further synthesized using the clock
divider circuitry. This clock can be divided by the N counter to generate
your
DCLK
output. The N divider supports all integer dividers between
1 and 16, as well as a 1.5 divider and a 2.5 divider. The duty cycle for all
clock divisions other than non-integer divisions is 50
%
(for the non-
integer dividers, the duty cycle will not be 50%). See
Figure 2–5
for a block
diagram of the clock divider unit.
Figure 2–5. Clock Divider Unit
The
DCLK
frequency is limited by the maximum
DCLK
frequency the
FPGA supports.
f
The maximum
DCLK
input frequency supported by the FPGA is
specified in the appropriate FPGA family chapter in the
Configuration
Handbook
.
Configuration Device
Clock Divider Unit
Divide
by N
External Clock
(Up to 133 MHz)
Internal Oscillator
10 MHz
33 MHz
50 MHz
66 MHz
DCLK
相關(guān)PDF資料
PDF描述
EPC16QC100 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC16QI100 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC8xxx 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC8QC100 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC8QI100 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
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