參數(shù)資料
型號(hào)： EP9315-IBZ
廠商： Cirrus Logic Inc
文件頁數(shù)： 79/106頁
文件大?。?/td> 0K
描述： IC ARM9 SOC ENH UNIV 352PBGA
標(biāo)準(zhǔn)包裝： 40
系列： EP9
核心處理器： ARM9
芯體尺寸： 16/32-位
速度： 200MHz
連通性： EBI/EMI，EIDE，以太網(wǎng)，I²C，IrDA，鍵盤/觸摸屏，PCMCIA，SPI，UART/USART，USB
外圍設(shè)備： AC'97，DMA，I²S，LCD，LED，MaverickKey，POR，PWM，WDT
輸入/輸出數(shù)： 16
程序存儲(chǔ)器類型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 352-BGA
包裝： 托盤
配用： 598-1144-ND - KIT DEVELOPMENT EP9315 ARM9
其它名稱： 598-1263
3-4
DS785UM1
Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
EP93xx User’s Guide
3
A double precision value requires all 64 bits:
A 32-bit integer is stored in the lower 32 bits of a 64-bit register and sign-extended when
written, provided the UI bit in the DSPSC is clear:
Hence, 32-bit integers may be used directly in calculations with 64-bit integers, which are
stored as:
3.1.5 Integer Saturation Arithmetic
By default, the co-processor treats all 32-bit and 64-bit integers as signed values and
automatically saturates the results of most integer operations and all conversions from
floating-point to integer format. Instructions that may saturate their results are:
CFADD32 and CFADD64
CFSUB32 and CFSUB64
CFMUL32 and CFMUL64
CFMAC32 and CFMSC32
CFCVTS32 and CFCVTD32
CFTRUNCS32 and CFTRUNCD32
This behavior, however, can be altered by setting the UI bit and the ISAT bit in the DSPSC.
With the UI bit clear (the default), 32-bit and 64-bit integer operations are treated as signed
with respect to overflow and underflow detection and saturation as well as compare
operations. Setting the UI bit causes the MaverickCrunch co-processor to treat all 32-bit and
64-bit integer operations as unsigned with respect to overflow, underflow, saturation, and
comparison.
Opcode
63
62
52 51
0
Sign
Exponent
Significand
Opcode
63
32
31
30
0
Sign Extension
Sign
Data
Opcode
63
62
0
Sign
Data
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