參數(shù)資料
型號: EP9315-IBZ
廠商: Cirrus Logic Inc
文件頁數(shù): 67/106頁
文件大?。?/td> 0K
描述: IC ARM9 SOC ENH UNIV 352PBGA
標(biāo)準(zhǔn)包裝: 40
系列: EP9
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 200MHz
連通性: EBI/EMI,EIDE,以太網(wǎng),I²C,IrDA,鍵盤/觸摸屏,PCMCIA,SPI,UART/USART,USB
外圍設(shè)備: AC'97,DMA,I²S,LCD,LED,MaverickKey,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器類型: ROMless
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 352-BGA
包裝: 托盤
配用: 598-1144-ND - KIT DEVELOPMENT EP9315 ARM9
其它名稱: 598-1263
DS785UM1
2-25
Copyright 2007 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
2
0x800C_022C
VIC2VectCntl11
Vector control 11 Register
N
0x800C_0230
VIC2VectCntl12
Vector control 12 Register
N
0x800C_0234
VIC2VectCntl13
Vector control 13 Register
N
0x800C_0238
VIC2VectCntl14
Vector control 14 Register
N
0x800C_023C
VIC2VectCntl15
Vector control 15 Register
N
0x800C_0FE0
VIC2PeriphID0
VIC Identification Register bits 7:0
N
0x800C_0FE4
VIC2PeriphID1
VIC Identification Register bits 15:8
N
0x800C_0FE8
VIC2PeriphID2
VIC Identification Register bits 23:16
N
0x800C_0FEC
VIC2PeriphID3
VIC Identification Register bits 31:24
N
0x800C_0FF0 - 0x800C_0FFC
Reserved
N
0x8081_xxxx
TIMER
Timer Registers
0x8081_0000
Timer1Load
Contains the initial value of the timer
N
0x8081_0004
Timer1Value
Gives the current value of the timer
N
0x8081_0008
Timer1Control
Provides enable/disable and mode configurations for the timer
N
0x8081_000C
Timer1Clear
Clears an interrupt generated by the timer
N
0x8081_0020
Timer2Load
Contains the initial value of the timer
N
0x8081_0024
Timer2Value
Gives the current value of the timer
N
0x8081_0028
Timer2Control
Provides enable/disable and mode configurations for the timer
N
0x8081_002C
Timer2Clear
Clears an interrupt generated by the timer
N
0x8081_0060 - 0x8081_0064
Reserved
0x8081_0080
Timer3Load
Contains the initial value of the timer
N
0x8081_0084
Timer3Value
Gives the current value of the timer
N
0x8081_0088
Timer3Control
Provides enable/disable and mode configurations for the timer
N
0x8081_008C
Timer3Clear
Clears an interrupt generated by the timer
N
0x8082_xxxx
I2S
I2S Registers
N
0x8082_0000
I2STXClkCfg
Transmitter clock configuration Register
N
0x8082_0004
I2SRXClkCfg
Receiver clock configuration Register
N
0x8082_0008
I2SGlSts
I2S Global Status Register. This reflects the status of the 3 RX
FIFOs and the 3 TX FIFOs
N
0x8082_000C
I2SGlCtrl
I2S Global Control Register
N
0x8082_0010
I2STX0Lft
Left Transmit data Register for channel 0
N
0x8082_0014
I2STX0Rt
Right Transmit data Register for channel 0
N
0x8082_0018
I2STX1Lft
Left Transmit data Register for channel 1
N
0x8082_001C
I2STX1Rt
Right Transmit data Register for channel 1
N
0x8082_0020
I2STX2Lft
Left Transmit data Register for channel 2
N
0x8082_0024
I2STX2Rt
Right Transmit data Register for channel 2
N
0x8082_0028
I2STXLinCtrlData
Transmit Line Control Register
N
0x8082_002C
I2STXCtrl
Transmit Control Register
N
0x8082_0030
I2STXWrdLen
Transmit Word Length
N
0x8082_0034
I2STX0En
TX0 Channel Enable
N
0x8082_0038
I2STX1En
TX1 Channel Enable
N
Table 2-8. Internal Register Map (Continued)
Address
Register Name
Register Description
SW
Lock
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