參數(shù)資料
型號： EP9315-IBZ
廠商： Cirrus Logic Inc
文件頁數(shù)： 50/106頁
文件大?。?/td> 0K
描述： IC ARM9 SOC ENH UNIV 352PBGA
標準包裝： 40
系列： EP9
核心處理器： ARM9
芯體尺寸： 16/32-位
速度： 200MHz
連通性： EBI/EMI，EIDE，以太網(wǎng)，I²C，IrDA，鍵盤/觸摸屏，PCMCIA，SPI，UART/USART，USB
外圍設(shè)備： AC'97，DMA，I²S，LCD，LED，MaverickKey，POR，PWM，WDT
輸入/輸出數(shù)： 16
程序存儲器類型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 352-BGA
包裝： 托盤
配用： 598-1144-ND - KIT DEVELOPMENT EP9315 ARM9
其它名稱： 598-1263
2-10
DS785UM1
Copyright 2007 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
2
2.2.8.1 Main AHB Bus Arbiter
This Main AHB Bus Arbiter controls bus master arbitration for the AHB bus. The AHB bus has
eight master interfaces:
ARM920T
DMA controller
USB hosts (USB1, 2, 3)
Ethernet MAC
LCD/Raster
Raster Hardware Cursor.
These interfaces have an order of priority that is linked closely with the power saving modes
Halt and Standby. These power saving modes force the Arbiter to grant the default bus
master, in this case, the ARM920T.
The order of priority of the bus masters, from highest to lowest, is shown in Table 2-1.
The priority of the arbiter may be programmed via the BusMstrArb register in the Clock and
State Controller. The arbiter can also be programmed to degrant one of these masters: DMA,
USB Host or Ethernet MAC if an interrupt (IRQ or FIQ) is pending or being serviced. This
prevents one of these masters from blocking important interrupt service routines. These
masters are thereby prevented from accessing the bus, that is, their bus requests are
masked until the IRQ/FIQ is removed (by the Interrupt Service Routine). After the IRQ/FIQ is
removed, their bus requests will again be recognized. The default is to program the arbiter so
that it does not degrant any of these masters.
In normal operation, when the ARM920T is granted the bus and a request to enter Halt mode
is received, the ARM920T is de-granted from the AHB bus. Any other master requesting the
bus during Halt mode (according to it’s priority) will be granted the bus. In the case of entry
into Standby mode, the dummy master will be granted the bus, which simply performs IDLE
transfers. In this way, all the masters except the ARM920T can be used during Halt mode, but
are shutdown upon entry into Standby mode.
Table 2-1. AHB Arbiter Priority Scheme
Priority
Number
PRIORITY 00
(Reset value)
PRIORITY 01
PRIORITY 10
PRIORITY 11
1
Raster Cursor
Raster
2
MAC
Raster Cursor
DMA
3
USB
MAC
DMA
MAC
4
DMA
USB
5
ARM920T
MAC
Raster Cursor
6
Raster
DMA
ARM920T
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