參數(shù)資料
型號： EP9315-IBZ
廠商： Cirrus Logic Inc
文件頁數(shù)： 49/106頁
文件大?。?/td> 0K
描述： IC ARM9 SOC ENH UNIV 352PBGA
標準包裝： 40
系列： EP9
核心處理器： ARM9
芯體尺寸： 16/32-位
速度： 200MHz
連通性： EBI/EMI，EIDE，以太網(wǎng)，I²C，IrDA，鍵盤/觸摸屏，PCMCIA，SPI，UART/USART，USB
外圍設(shè)備： AC'97，DMA，I²S，LCD，LED，MaverickKey，POR，PWM，WDT
輸入/輸出數(shù)： 16
程序存儲器類型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 352-BGA
包裝： 托盤
配用： 598-1144-ND - KIT DEVELOPMENT EP9315 ARM9
其它名稱： 598-1263
DS785UM1
2-9
Copyright 2007 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
2
A write data bus is used to move data from the master to a slave, while a read data bus is
used to move data from a slave to the master. Every transfer consists of:
An address and control cycle
One or more cycles for the data.
In normal operation a master is allowed to complete all the transfers in a particular burst
before the arbiter grants another master access to the bus. However, in order to avoid
excessive arbitration latencies, it is possible for the arbiter to break up a burst, and, in such
cases, the master must re-arbitrate for the bus in order to complete the remaining transfers in
the burst.
2.2.7 Memory and Bus Access Errors
There are several possible sources of access errors:
Reads to reserved or undefined register memory addresses will return indeterminate
data. Writes to reserved or undefined memory addresses are generally ignored, but this
behavior is not guaranteed. Many register addresses are not fully decoded, so aliasing
may occur. Addresses and memory ranges listed as Reserved should not be accessed;
access behavior to these regions is not defined
Access to non-existent registers or memory may result in a bus error
Any access to the APB control register space will complete normally, as these devices
have no means of signaling an error
Access to non-existent AHB or APB registers may result in a bus error, depending on the
device and nature of the error. Device specific access rules are defined in the device
descriptions
External memory access is controlled by the Static Memory Controller (SMC) or the
Synchronous Dynamic RAM (SDRAM) controller. In general, access to non-existent
external memory will complete normally, with reads returning random false data.
2.2.8 Bus Arbitration
The arbitration mechanism is used to ensure that only one master has access to the bus that
it controls at any one time. The Arbiter performs this function by observing a number of
different requests to use the bus, and then deciding which is currently the highest priority
master requesting the bus.
The arbitration scheme can be broken down into three main areas:
The main AHB system bus Arbiter
The SDRAM slave interface Arbiter
The EBI bus Arbiter
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