參數(shù)資料
型號: EP20K200BC784-2
廠商: ALTERA CORP
元件分類: PLD
英文描述: LOADABLE PLD, PBGA784
文件頁數(shù): 7/65頁
文件大?。?/td> 781K
代理商: EP20K200BC784-2
Altera Corporation
37
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Cascade chains longer than 10 LEs are implemented automatically by
linking LABs together. For enhanced fitting, a long cascade chain skips
alternate LABs in a MegaLAB structure. A cascade chain longer than one
LAB skips either from an even-numbered LAB to the next even-numbered
LAB, or from an odd-numbered LAB to the next odd-numbered LAB. For
example, the last LE of the first LAB in the upper-left MegaLAB structure
carries to the first LE of the third LAB in the MegaLAB structure. Figure 7
shows how the cascade function can connect adjacent LEs to form
functions with a wide fan-in.
Figure 7. APEX 20K Cascade Chain
LE Operating Modes
The APEX 20K LE can operate in one of the following three modes:
s
Normal mode
s
Arithmetic mode
s
Counter mode
Each mode uses LE resources differently. In each mode, seven available
inputs to the LE—the four data inputs from the LAB local interconnect,
the feedback from the programmable register, and the carry-in and
cascade-in from the previous LE—are directed to different destinations to
implement the desired logic function. LAB-wide signals provide clock,
asynchronous clear, asynchronous preset, asynchronous load,
synchronous clear, synchronous load, and clock enable control for the
register. These LAB-wide signals are available in all LE modes.
LE1
LUT
LE2
LUT
d[3..0]
d[7..4]
d[(4
n – 1)..(4n – 4)]
d[3..0]
d[7..4]
LE
n
LE1
LE2
LE
n
LUT
AND Cascade Chain
OR Cascade Chain
d[(4
n – 1)..(4n – 4)]
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