參數(shù)資料
型號： EP20K200BI784-1
廠商： ALTERA CORP
元件分類： PLD
英文描述： LOADABLE PLD, PBGA784
文件頁數(shù)： 1/65頁
文件大小： 781K
代理商： EP20K200BI784-1
Altera Corporation
23
APEX 20K
Programmable Logic
Device Family
May 1999, ver. 2
Data Sheet
A-DS-APEX20K-02
Features...
s
Industry’s first programmable logic device (PLD) incorporating
System-on-a-Programmable-ChipTM integration
–
MultiCoreTM architecture integrating look-up table (LUT) logic,
product-term logic, and embedded memory
–
Embedded system block (ESB) implementation of product-term
logic used for combinatorial-intensive functions
Preliminary
Information
–
LUT logic used for register-intensive functions
–
ESB used to implement memory functions, including first-in
first-out (FIFO) buffers, dual-port RAM, and content-
addressable memory (CAM)
s
High density
–
100,000 to 1 million typical gates (see Table 1)
–
Up to 42,240 logic elements (LEs)
–
Up to 540,672 RAM bits that can be used without reducing
available logic
–
Up to 4,224 product-term-based macrocells
Notes:
(1)
The embedded IEEE Std. 1149.1 JTAG boundary-scan circuitry contributes up to 52,130 additional gates.
(2)
This information is preliminary.
Table 1. APEX 20K Device Features
Feature
EP20K100E
EP20K100
EP20K160E EP20K200E
EP20K200
EP20K300E EP20K400E
EP20K400
EP20K600E EP20K1000E
Maximum
system gates
263,000
404,000
526,000
728,000
1,052,000
1,537,000
2,670,000
Typical gates
106,000
163,000
211,000
293,000
423,000
618,000
1,073,000
LEs
4,160
6,400
8,320
11,520
16,640
24,320
42,240
ESBs
26
40
52
72
104
152
264
Maximum
RAM bits
53,248
81,920
106,496
147,456
212,992
311,296
540,672
Maximum
macrocells
416
640
832
1,152
1,664
2,432
4,224
Maximum
user I/O pins
252
320
382
420
502
620
780
相關PDF資料
PDF描述
EP20K200BI784-2 LOADABLE PLD, PBGA784
EP20K200BI784-3 LOADABLE PLD, PBGA784
EP20K200EFC784-1 LOADABLE PLD, PBGA784
EP20K200EFC784-2 LOADABLE PLD, PBGA784
EP20K200EFC784-3 LOADABLE PLD, PBGA784
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