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Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 5. APEX 20K Logic Element
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. The register’s clock and clear control signals can be driven by
global signals, general-purpose I/O pins, or any internal logic. For
combinatorial functions, the register is bypassed and the output of the
LUT drives the outputs of the LE.
The LE has two outputs that drive the local, MegaLAB, or FastTrack
Interconnect routing structure. Each output can be driven independently
by the LUT’s or register’s output. For example, the LUT can drive one
output while the register drives the other output. This feature, called
register packing, improves device utilization because the register and the
LUT can be used for unrelated functions. The LE can also drive out
registered and unregistered versions of the LUT output.
labclk1
labclk2
labclr1
labclr2
Carry-In
Clock &
Clock Enable
Select
Carry-Out
Look-Up
Table
(LUT)
Carry
Chain
Cascade
Chain
Cascade-In
Cascade-Out
To FastTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
To FastTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
Programmable
Register
PRN
CLRN
D
Q
ENA
Register Bypass
Packed
Register Select
Chip-Wide
Reset
labclkena1
labclkena2
Synchronous
Load & Clear
Logic
LAB-wide
Synchronous
Load
LAB-wide
Synchronous
Clear
Asynchronous
Clear/Preset/
Load Logic
data1
data2
data3
data4