參數(shù)資料
型號(hào)： EP20K200BC784-2
廠(chǎng)商： ALTERA CORP
元件分類(lèi)： PLD
英文描述： LOADABLE PLD, PBGA784
文件頁(yè)數(shù)： 3/65頁(yè)
文件大?。?/td> 781K
代理商： EP20K200BC784-2
Altera Corporation
33
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
The LAB-wide control signals can be generated from the LAB local
interconnect, global signals, and dedicated clock pins. The inherent low
skew of the FastTrack Interconnect enables it to be used for clock
distribution. Figure 4 shows the LAB control signal generation circuit.
Figure 4. LAB Control Signal Generation
Notes:
(1)
APEX 20KE devices have four dedicated clocks.
(2)
The LABCLR1 and LABCLR2 signals also control asynchronous load and asynchronous preset for LEs within the
LAB.
(3)
The SYNCCLR signal can be generated by the local interconnect or global signals.
Logic Element
The logic element (LE), the smallest unit of logic in the APEX 20K
architecture, is compact and provides efficient logic usage. Each LE
contains a four-input LUT, which is a function generator that can quickly
implement any function of four variables. In addition, each LE contains a
programmable register and carry and cascade chains. Each LE drives the
local interconnect, MegaLAB interconnect, and FastTrack Interconnect
routing structures. See Figure 5.
SYNCCLR
or LABCLK2
(3)
SYNCLOAD
or LABCLKENA2
LABCLK1
LABCLKENA1
LABCLR2
(2)
LABCLR1
(2)
Dedicated
Clocks
Global
Signals
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
2 or 4
(1)
4
相關(guān)PDF資料
PDF描述
EP20K200BC784-3 LOADABLE PLD, PBGA784
EP20K200BI784-1 LOADABLE PLD, PBGA784
EP20K200BI784-2 LOADABLE PLD, PBGA784
EP20K200BI784-3 LOADABLE PLD, PBGA784
EP20K200EFC784-1 LOADABLE PLD, PBGA784
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