參數(shù)資料
型號(hào): EP20K200BC784-2
廠商: ALTERA CORP
元件分類: PLD
英文描述: LOADABLE PLD, PBGA784
文件頁數(shù): 6/65頁
文件大?。?/td> 781K
代理商: EP20K200BC784-2
36
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 6. APEX 20K Carry Chain
Cascade Chain
With the cascade chain, the APEX 20K architecture can implement
functions with a very wide fan-in. Adjacent LUTs can compute portions
of a function in parallel; the cascade chain serially connects the
intermediate values. The cascade chain can use a logical AND or logical OR
(via De Morgan’s inversion) to connect the outputs of adjacent LEs. Each
additional LE provides four more inputs to the effective width of a
function, with a short cascade delay. Cascade chain logic can be created
automatically by the Quartus Compiler during design processing, or
manually by the designer during design entry.
LUT
a1
b1
Carry Chain
s1
LE1
Register
a2
b2
Carry Chain
s2
LE2
Register
Carry Chain
s
n
LE
n
Register
a
n
b
n
Carry Chain
Carry-Out
LE
n + 1
Register
Carry-In
LUT
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