Altera Corporation
6–63
June 2006
Stratix GX Device Handbook, Volume 1
DC & Switching Characteristics
tOUTDUTY
Duty cycle for external clock output
(when set to 50%)
45
55
%
tJITTER
Period jitter for external clock output
(5)±100 ps for >200 MHz outclk
±20 mUI for <200 MHz outclk
ps or
mUI
tCONFIG5,6
Time required to reconfigure the scan
chains for PLLs 5 and 6
289/fSCANCLK
tCONFIG11,12
Time required to reconfigure the scan
chains for PLLs 11 and 12
193/fSCANCLK
tSCANCLK
scanclk
22
MHz
tDLOCK
Time required to lock dynamically (after
switchover or reconfiguring any non-
post-scale counters/delays)
(6)100
μs
tLOCK
Time required to lock from end of
device configuration
10
400
μs
fVCO
PLL internal VCO operating range
300
MHz
tLSKEW
Clock skew between two external clock
outputs driven by the same counter
±50
ps
tSKEW
Clock skew between two external clock
outputs driven by the different counters
with the same settings
±75
ps
fSS
Spread spectrum modulation frequency
30
150
kHz
% spread
Percentage spread for spread
0.4
0.5
0.6
%
tARESET
Minimum pulse width on areset
signal
10
ns
Table 6–89. Enhanced PLL Specifications for -6 Speed Grades
(Part 1 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
fIN
Input clock frequency
650
MHz
fINDUTY
Input clock duty cycle
40
60
%
fEINDUTY
External feedback clock input duty
cycle
40
60
%
tINJITTER
Input clock period jitter
ps
tEINJITTER
External feedback clock period jitter
ps
tFCOMP
External feedback clock compensation
6ns
Table 6–88. Enhanced PLL Specifications for -5 Speed Grades (Part 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit