4–114
Altera Corporation
Stratix GX Device Handbook, Volume 1
February 2005
I/O Structure
■
LVDS
■
LVPECL
■
3.3-V PCML
■
HyperTransport
■
Differential HSTL (on input/output clocks only)
■
Differential SSTL (on output column clock pins only)
■
GTL/GTL+
■
1.5-V HSTL class I and II
■
1.8-V HSTL Class I and II
■
SSTL-3 class I and II
■
SSTL-2 class I and II
■
SSTL-18 class I and II
■
CTT
Table 4–27 describes the I/O standards supported by Stratix GX devices.
Table 4–27. Stratix GX Supported I/O Standards (Part 1 of 2)
I/O Standard
Type
Input Reference
Voltage (VREF)
(V)
Output Supply
Voltage (VCCIO)
(V)
Board
Termination
Voltage (VTT)
(V)
LVTTL
Single-ended
N/A
3.3
N/A
LVCMOS
Single-ended
N/A
3.3
N/A
2.5 V
Single-ended
N/A
2.5
N/A
1.8 V
Single-ended
N/A
1.8
N/A
1.5 V
Single-ended
N/A
1.5
N/A
3.3-V PCI
Single-ended
N/A
3.3
N/A
3.3-V PCI-X 1.0
Single-ended
N/A
3.3
N/A
LVDS
Differential
N/A
3.3
N/A
LVPECL
Differential
N/A
3.3
N/A
3.3-V PCML
Differential
N/A
3.3
N/A
HyperTransport
Differential
N/A
2.5
N/A
Differential
0.75
1.5
0.75
Differential
1.25
2.5
1.25
GTL
Voltage-referenced
0.8
N/A
1.20
GTL+
Voltage-referenced
1.0
N/A
1.5
1.5-V HSTL class I and II
Voltage-referenced
0.75
1.5
0.75
1.8-V HSTL class I and II
Voltage-referenced
0.9
1.8
0.9
SSTL-18 class I and II
Voltage-referenced
0.90
1.8
0.90
SSTL-2 class I and II
Voltage-referenced
1.25
2.5
1.25