參數(shù)資料
型號(hào)： EM773FHN33,551
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 8/51頁(yè)
文件大?。?/td> 0K
描述： IC ENERGY METER ARM 32VQFN
其它有關(guān)文件： EM773 Energy Metering IC Training
特色產(chǎn)品： EM773 Energy Metering IC
標(biāo)準(zhǔn)包裝： 260
核心處理器： ARM? Cortex?-M0
芯體尺寸： 32-位
速度： 48MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，WDT
輸入/輸出數(shù)： 25
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.6 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 32-VQFN 裸露焊盤(pán)
包裝： 托盤(pán)
配用： 568-6681-ND - BOARD EVAL EM773 METER EU PLUG
568-6680-ND - BOARD EVAL EM773 METER US PLUG
其它名稱(chēng)： 568-5213
EM773
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 3 January 2012
16 of 51
NXP Semiconductors
EM773
Energy metering IC
7.15.1.2
System oscillator
The system oscillator can be used as the clock source for the CPU, with or without using
the PLL.
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL.
7.15.1.3
Watchdog oscillator
The watchdog oscillator can be used as a clock source that directly drives the CPU, the
watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is
programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and
temperature is
40 %.
7.15.2 System PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within
its frequency range while the PLL is providing the desired output frequency. The PLL
output frequency must be lower than 100 MHz. The output divider may be set to divide by
2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is
insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed
following a chip reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.
The PLL settling time is 100
s.
7.15.3 Clock output
The EM773 features a clock output function that routes the IRC oscillator, the system
oscillator, the watchdog oscillator, or the main clock to an output pin.
7.15.4 Wake-up process
The EM773 begin operation at power-up and when awakened from Deep power-down
mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation
to resume quickly. If the system oscillator or the PLL is needed by the application,
software will need to enable these features and wait for them to stabilize before they are
used as a clock source.
7.15.5 Power control
The EM773 support a variety of power control features. There are three special modes of
processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode.
The CPU clock rate may also be controlled as needed by changing clock sources,
reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a
trade-off of power versus processing speed based on application requirements. In
addition, a register is provided for shutting down the clocks to individual on-chip
peripherals, allowing fine tuning of power consumption by eliminating all dynamic power
use in any peripherals that are not required for the application. Selected peripherals have
their own clock divider which provides even better power control.
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