參數(shù)資料
型號: EM773FHN33,551
廠商: NXP Semiconductors
文件頁數(shù): 30/51頁
文件大?。?/td> 0K
描述: IC ENERGY METER ARM 32VQFN
其它有關(guān)文件: EM773 Energy Metering IC Training
特色產(chǎn)品: EM773 Energy Metering IC
標(biāo)準(zhǔn)包裝: 260
核心處理器: ARM? Cortex?-M0
芯體尺寸: 32-位
速度: 48MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 25
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤
包裝: 托盤
配用: 568-6681-ND - BOARD EVAL EM773 METER EU PLUG
568-6680-ND - BOARD EVAL EM773 METER US PLUG
其它名稱: 568-5213
EM773
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 3 January 2012
36 of 51
NXP Semiconductors
EM773
Energy metering IC
10.5 I/O pins
[1]
Applies to standard port pins and RESET pin.
10.6 I2C-bus
[1]
See the I2C-bus specification UM10204 for details.
[2]
Parameters are valid over operating temperature range unless otherwise specified.
[3]
tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission
and the acknowledge.
[4]
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
[5]
Cb = total capacitance of one bus line in pF.
Table 12.
Dynamic characteristic: I/O pins[1]
Tamb = 40 C to +85 C; 3.0 V VDD 3.6 V.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tr
rise time
pin
configured as
output
3.0
-
5.0
ns
tf
fall time
pin
configured as
output
2.5
-
5.0
ns
Table 13.
Dynamic characteristic: I2C-bus pins[1]
Tamb = 40 C to +85 C.[2]
Symbol
Parameter
Conditions
Min
Max
Unit
fSCL
SCL clock
frequency
Standard-mode
0
100
kHz
Fast-mode
0
400
kHz
Fast-mode Plus
0
1
MHz
tf
fall time
of both SDA and
SCL signals
Standard-mode
-
300
ns
Fast-mode
20 + 0.1
C
b
300
ns
Fast-mode Plus
-
120
ns
tLOW
LOW period of
the SCL clock
Standard-mode
4.7
-
s
Fast-mode
1.3
-
s
Fast-mode Plus
0.5
-
s
tHIGH
HIGH period of
the SCL clock
Standard-mode
4.0
-
s
Fast-mode
0.6
-
s
Fast-mode Plus
0.26
-
s
tHD;DAT
data hold time
Standard-mode
0
-
s
Fast-mode
0
-
s
Fast-mode Plus
0
-
s
tSU;DAT
data set-up
time
Standard-mode
250
-
ns
Fast-mode
100
-
ns
Fast-mode Plus
50
-
ns
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