參數(shù)資料
型號: ELANSC300-33KC
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述: 32-BIT, 33 MHz, MICROCONTROLLER, PQFP208
封裝: SHRINK, PLASTIC, QFP-208
文件頁數(shù): 50/139頁
文件大?。?/td> 1388K
代理商: ELANSC300-33KC
50
élanSC300 Microcontroller Data Sheet
P R E L I M I N A R Y
Notes:
Refer to Index 70h, bit 0, in the
élan
TM
SC300 Microcontroller Programmer’s Reference Manual
, order #18470
for information on how to select SRAM versus DRAM.
PCMCIA Slots
The élanSC300 microcontroller supports two
revision 2.1 PCMCIA slots.
MMS mapping logic is used to access the PCMCIA
memory address space. Up to twelve 16-Kbyte pages
of the CPU’s address space are mapped into windows
of PCMCIA memory address space.
Depending on the system requirements, the address
and data lines to the PCMCIA slots may or may not re-
quire external buffers (see Figure 7 on page 64). For
more information, see Chapter 2 in the élan
TM
SC300
Microcontroller Programmer’s Reference Manual
,
order #18470. Also see the
élan
TM
SC300 and
élanSC310 Microcontrollers Memory Management Ap-
plication Note
, order #21823 and the
Using a PCMCIA
Card as a Boot ROM on an élan
TM
SC300 Microcon-
troller Design Application Note
, order #21824.
The PMU Modes and Clock Generators
The Power Management Unit (PMU) monitors all sys-
tem activities (e.g., keyboard, screen, and disk events),
and, based on the state of the system, determines in
which operating mode
the system should be running.
The PMU supports six operating modes, each defined
by a different combination of CPU and peripheral oper-
ation, as shown in the list that follows.
1.
High-Speed PLL.
All clocks are at their fastest
speed and all peripherals are powered up. This is
the mode the system enters when activity is de-
tected by the PMU.
2.
Low-Speed PLL.
The internal CPU clock is re-
duced to a maximum of 4.608 MHz. All other clocks
and peripherals operate at full speed. This is the
first level of power conservation; it is entered after a
specified elapsed time with no activity.
3.
Doze.
The second level of power conservation. The
CPU, system, and DMA clocks are stopped. The
high-speed PLL is turned off. This mode is entered
after a specified elapsed time with no activity.
4.
Sleep.
Additional clocks and peripherals are
stopped after additional inactivity has been de-
tected. The exact parameters can be programmed.
The Low-Speed PLL can be left on, so a quick star-
tup is possible.
5.
Suspend.
Virtually all of the system is shut down,
including all clocks, the 8254 timer, and the Phase
Locked Loops (a programmable recovery time is
associated with this mode). The 32.768-kHz clock
input is still running.
6.
Off.
This level is virtually the same as Suspend
mode. Two outputs can be programmed to change
state when the transition from Suspend mode to Off
mode occurs. DRAM refresh can be disabled in
OFF mode.
In addition, the élanSC300 microcontroller can man-
age the power consumption of peripheral devices. This
control can be forced upon entering a specific operat-
ing mode or it can be handled directly by firmware. The
élanSC300 microcontroller PMU controls five power
management control (PMC) pins that are controlled by
the operating modes.
Clock Generation
The élanSC300 microcontroller requires only one
32.768-kHz clock input that is used to generate all
other clock frequencies required by the system. This
32.768-kHz clock input is provided through the X32IN
and X32OUT pins and the crystal oscillator circuit. This
input frequency is then used to internally drive multiple
Phase-Locked Loops that create all necessary fre-
quencies.
The clock rate that is used to drive the internal CPU is
determined by the mode of operation of the élanSC300
microcontroller.
The clock generation, control, and distribution scheme
are detailed in Figure 1 and Figure 2, which follow.
Table 19.
SRAM Wait State Select Logic
Configuration
Number of Wait States
SRAM Speed
Index 63h
Bit 4
Index 66h
Bits 1 and 0
Read
Write
20 MHz
25 MHz
33 MHz
x
0
1
0 0
0 1
0 1
0
1
2
1
1
2
45 ns
80 ns
120 ns
35 ns
55 ns
100 ns
25 ns
35 ns
70 ns
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