參數(shù)資料
型號： EDE5108AHSE-6E-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 64M X 8 DDR DRAM, 0.45 ns, PBGA60
封裝： ROHS COMPLIANT, FBGA-60
文件頁數(shù)： 8/64頁
文件大小： 871K
代理商： EDE5108AHSE-6E-E
Datasheet
DD2.x
PowerPC 750CL Microprocessor
Preliminary
Electrical and Thermal Characteristics
Page 16 of 65
750cl_ds_body.fm.2.4
May 29, 2007
Table 3-3. Package Thermal Characteristics
Characteristic
Symbol
Value
Unit
FCPBGA package thermal resistance, junction-to-case thermal resistance (typ-
ical)
θ
JC
2
°C/W
FCPBGA package thermal resistance, junction-to-lead thermal resistance (typi-
cal)
θ
JB
13
°C/W
Note:
θ
JC is the internal resistance from the junction to the top surface of the package. A heatsink is generally required to ensure that
the die junction temperature is maintained within the limits defined in Table 3-2, Recommended Operating Conditions, on page 15.
Note: Thermal resistance values are based on modeling only.
Table 3-4. DC Electrical Specifications
See Table 3-2 on page 15 for recommended operating conditions.
Characteristic
Symbol
Value
Unit
Notes
Min.
Max.
Input high voltage
VIH (1.15 V)
0.75
—
V
VIH (1.8 V)
1.20
—
V
Input low voltage
VIL (1.15 V)
—0.40
V
VIL (1.8 V)
—0.60
V
Input leakage current, VIN = applies to all OVDD levels
IIN
—10
μA
Hi-Z (off state) leakage current, VIN = applies to all OVDD levels
ITSI
—10
μA
Output high voltage, IOH = -4 mA
VOH (1.15 V)
0.90
—
V
Output high voltage, IOH = -4 mA
VOH (1.8 V)
1.30
—
V
Output low voltage, IOL = 4 mA
VOL (1.15 V)
—0.30
V
Output low voltage, IOL = 4 mA
VOL (1.8 V)
—0.40
V
Capacitance, VIN = 0 V, f = 1 MHz
CIN
—5
pF
Single-Ended SYSCLK Clock Specifications
SYSCLK input high voltage
VIH (1.15 V)
0.8
—
V
VIH (1.8 V)
1.20
—
V
SYSCLK input low voltage
VIL (1.15 V)
—0.30
V
VIL (1.8 V)
—0.30
V
Differential SYSCLK Clock Specifications
SYSCLK and SYSCLK single-ended swing
CSVSW
175
450
mV (P - P)
SYSCLK - SYSCLK differential swing
CDVSW
350
900
mV (P - P)
SYSCLK and SYSCLK differential cross point
CDVCP
400
750
mV
SYSCLK and SYSCLK input capacitance
CCIN
—5
pF
Notes:
1. Capacitance values are guaranteed by design and characterization and are not tested.
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