參數(shù)資料
型號(hào)： EDE5108AHSE-6E-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 64M X 8 DDR DRAM, 0.45 ns, PBGA60
封裝： ROHS COMPLIANT, FBGA-60
文件頁(yè)數(shù)： 37/64頁(yè)
文件大?。?/td> 871K
代理商： EDE5108AHSE-6E-E
Datasheet
DD2.x
PowerPC 750CL Microprocessor
Preliminary
System Design Information
Page 42 of 65
750cl_ds_body.fm.2.4
May 29, 2007
5.5 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OVDD. Unused active high inputs should be connected to
GND. All no-connect (NC) signals must remain unconnected.
Power and ground connections must be made to all external VDD, OVDD, AVDD, and GND pins of the 750CL.
5.6 Die Temperature Monitor
The PowerPC 750CL microprocessor features an on-board temperature sensing diode for determining the
chip junction temperature, TJ. A schematic of the thermal diode is shown in Figure 5-3. The thermal diode is
placed within the die circuitry in proximity of the hottest area on the die. Its terminals are then connected to
pins THRMD1 and THRMD2.
The procedure for monitoring temperature involves forcing a 100
μA current through the diode and measuring
the resultant voltage. The measured voltage can then be used to interpolate the junction temperature using
two reference voltage/temperature data points that are preset at the factory. The reference points are stored
in the 750CL Thermal Diode Calibration Registers, TDCL and TDCH. TDCL contains the diode voltage from
forcing 100
μA through the diode at a low temperature (both voltage and temperature included in the
register). TDCH contains the diode voltage from forcing 100
μA through the diode at a high temperature (also
included in the register). Consult the IBM PowerPC 750CL RISC Microprocessor User’s Manual for the
specific format of the registers. The graph in Figure 5-4 on page 43 illustrates the procedure for determining
the chip junction temperature based on the user's voltage measurement and the reference points provided in
the calibration registers.
Figure 5-3. Thermal Diode Schematic
VDD
THRMD1
THRMD2
PAD
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