參數(shù)資料
型號(hào): EBE20RE4AAFA-4A-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 1 Rank)
中文描述: 256M X 72 DDR DRAM MODULE, 0.6 ns, DMA240
封裝: LEAD FREE, DIMM-240
文件頁(yè)數(shù): 14/22頁(yè)
文件大小: 191K
代理商: EBE20RE4AAFA-4A-E
EBE20RE4AAFA
Data Sheet E0440E30 (Ver. 3.0)
14
ODT DC Electrical Characteristics (TC = 0
°C
to +85
°
C, VDD, VDDQ = 1.8V
±
0.1V)
(DDR2 SDRAM Component Specification)
Parameter
Symbol
min.
typ.
max.
Unit
Note
Rtt effective impedance value for EMRS (A6, A2)
=
0, 1
;
75
Rtt1(eff)
60
75
90
1
Rtt effective impedance value for EMRS (A6, A2)
=
1, 0
;
150
Rtt2(eff)
120
150
180
1
Deviation of VM with respect to VDDQ/2
VM
3.75
+
3.75
%
1
Note: 1. Test condition for Rtt measurements.
Measurement Definition for Rtt(eff)
Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH(AC)) and I(VIL(AC)) respectively.
VIH(AC), and VDDQ values defined in SSTL
_
18.
VIH(AC)
VIL(AC)
I(VIH(AC))
I(VIL(AC))
Rtt(eff) =
Measurement Definition for VM
Measure voltage (VM) at test pin (midpoint) with no load.
VM =
×
VM
VDDQ
×
100%
1
OCD Default Characteristics (TC = 0
°C
to +85
°
C, VDD, VDDQ = 1.8V
±
0.1V)
(DDR2 SDRAM Component Specification)
Parameter
min
typ.
max.
Unit
Notes
Output impedance
12.6
18
23.4
1
Pull-up and pull-down mismatch
0
4
1, 2
Output slew rate
1.5
4.5
V/ns
3, 4
Notes: 1. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV;
(VOUT
VDDQ)/IOH must be less than 23.4
for values of VOUT between VDDQ and VDDQ
280mV.
Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV;
VOUT/IOL must be less than 23.4
for values of VOUT between 0V and 280mV.
2. Mismatch is absolute value between pull up and pull down, both are measured at same temperature and
voltage.
3. Slew rate measured from VIL(AC) to VIH(AC).
4. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate
as measured from AC to AC. This is guaranteed by design and characterization.
Pin Capacitance (TA = 25°C, VDD = 1.8V ± 0.1V)
Parameter
Symbol
Pins
min.
max.
Unit
Note
Input capacitance
CI1
Address, /RAS, /CAS,
/WE, /CS, CKE, ODT
CK, /CK
2.5
3.5
pF
1
Input capacitance
Data and DQS input/output
capacitance
Notes: 1. Register component specification.
2. PLL component specification.
3. DDR2 SDRAM component specification.
CI2
2
3
pF
2
CO
DQ, DQS, /DQS, CB
2.5
3.5
pF
3
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