- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384274 > EBE20RE4AAFA-4A-E (ELPIDA MEMORY INC) 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 1 Rank) PDF資料下載
參數(shù)資料
| 型號： | EBE20RE4AAFA-4A-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 1 Rank) |
| 中文描述： | 256M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封裝： | LEAD FREE, DIMM-240 |
| 文件頁數(shù)： | 12/22頁 |
| 文件大?。?/td> | 191K |
| 代理商： | EBE20RE4AAFA-4A-E |
EBE20RE4AAFA
Data Sheet E0440E30 (Ver. 3.0)
12
Parameter
Symbol
Grade
max.
Unit
Test condition
tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self Refresh Mode;
CK and /CK at 0V;
CKE
≤
0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD (IDD)
1
×
tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
tRCD = 1
×
tCK (IDD);
CKE is H, CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4R;
Auto-refresh current
IDD5
-5C
-4A
TBD
6970
mA
Self-refresh current
IDD6
-5C
-4A
TBD
320
mA
Operating current
(Bank interleaving)
IDD7
-5C
-4A
TBD
7030
mA
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS. IDD values must be met with all
combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN
≤
VIL (AC) (max.)
H is defined as VIN
≥
VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-533
DDR2-400
Parameter
4-4-4
3-3-3
Unit
CL(IDD)
4
3
tCK
tRCD(IDD)
15
15
ns
tRC(IDD)
60
60
ns
tRRD(IDD)
7.5
7.5
ns
tCK(IDD)
3.75
5
ns
tRAS(min.)(IDD)
45
45
ns
tRAS(max.)(IDD)
70000
70000
ns
tRP(IDD)
15
15
ns
tRFC(IDD)
127.5
127.5
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EBE20RE4AAFA-5C-E | 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 1 Rank) |
| EBE21RD4ABHA-5C-E | GT 7C 7#12 PIN PLUG |
| EBE21RD4AEFA-5C-E | 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks) |
| EBE21RD4AGFA-4A-E | 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks) |
| EBE21RD4AGFA-5C-E | 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EBE20RE4AAFA-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 1 Rank) |
| EBE20RE4ABFA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR2 SDRAM DIMM |
| EBE20RE4ABFA-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR2 SDRAM DIMM |
| EBE20RE4ABFA-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR2 SDRAM DIMM |
| EBE20RE4ABFA-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR2 SDRAM DIMM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。