參數(shù)資料
型號: EB402
英文描述: EB402 Evaluation Board user's guide 7/01
中文描述: EB402評估板用戶指南7月1日
文件頁數(shù): 42/84頁
文件大小: 1014K
代理商: EB402
Memory and Memory-Mapped Peripherals
3-25
3.4.2.6 UART Memory Space
Although not memory, the on-board UART is mapped into the LSI402ZX
peripheral memory space. It is enabled by PCS0N. Accessing peripheral
memory requires wait states. These calculations are shown in
3.4.2.7 External Expansion Interface (EEI)
The XBUS control, address, and data signals are buffered and routed to
two external connectors: the control signals go to J8; the address and
data signals go to J11. These connectors provide a physical interface for
mounting a daughterboard that can have additional external memory or
peripherals. The EEI daughterboard can be used as instruction space,
data space, or peripheral space.
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