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參數(shù)資料
| 型號(hào)： | EB402 |
| 英文描述： | EB402 Evaluation Board user＇s guide 7/01 |
| 中文描述： | EB402評(píng)估板用戶指南7月1日 |
| 文件頁數(shù)： | 36/84頁 |
| 文件大?。?/td> | 1014K |
| 代理商： | EB402 |
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Memory and Memory-Mapped Peripherals
3-19
3.3.5 External Expansion Interface (EEI)
The EEI allows extending the LSI402ZX XBUS to an external system.
For example, the EEI allows the LSI402ZX to control off-board memory
and peripherals.
The XBUS control, address, and data signals are buffered and connected
to two external connectors; J8 has the control signals; J11 has the
address and data signals. These connectors provide a physical interface
for mounting a daughterboard that can provide additional external memory
or peripherals. The EEI uses the LSI402ZX HOLD/HOLDA protocol.
3.3.6 Discrete LED Display
After booting from the on-chip ROM, the LSI402ZX runs through an internal
diagnostic program and writes the self-test results into operand registers.
The results are also sent to the 74LVC574A registers, using PCS3N for the
write select. These registers drive 16 LEDs that display the results.
A write to anywhere in address space 0xFF00 to 0xFFFF will access the
LEDs because they are controlled by write select PCS3N. The LEDs are
numbered LD1 (LSB) to LD16 (MSB). These active-LOW LEDs are
always enabled; write 0b0 to illuminate an LED; write 0b1 to turn it off.
No wait states are required to latch data into the 74LVC574A registers.
PCS3N is programmed for zero wait states by setting register
p3wait = 0x0000.
3.4 Memory and Memory-Mapped Peripherals
The EB402 memory consists of internal memory, which is inside the
LSI402ZX, and external memory, which can be on-board or off-board.
On-board external memory consists of ash memory, asynchronous
SRAM, and SBSRAM. The EEI allows placing additional external
memory on a daughterboard. Refer to Appendix A, Schematics,for
EB402 memory interface details. The following memory topics are
described in this section:
Internal Memory
External Memory and Memory-Mapped Peripherals
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