參數(shù)資料
型號: EB402
英文描述: EB402 Evaluation Board user's guide 7/01
中文描述: EB402評估板用戶指南7月1日
文件頁數(shù): 27/84頁
文件大小: 1014K
代理商: EB402
External Interfaces
3-11
3.3.1 JTAG Interfaces
The EB402 provides two JTAG interfaces to support emulators from
Corelis and Macraigor.
3.3.1.1 Corelis JTAG Interface
The Corelis JTAG connector, J7, provides a physical interface to the host
computer. The JTAG interface signals are buffered and connected to a
10-pin, low-prole header. Figure 3.2 shows the header and the signals
that connect to its pins.
Figure 3.2
Corelis JTAG Connector
The Corelis JTAG interface works with the SDK software tools and the
Corelis JTAG emulator (installed on the host computer) to provide
full-speed, in-circuit emulation.
3.3.1.2 Macraigor JTAG Interface
The Macraigor JTAG connector, J5, provides a physical interface to the
Macraigor JTAG controller installed on the host computer. The JTAG
interface signals are buffered and connected to a 16-pin, low-profile header.
Figure 3.3 shows the header and the signals that connect to its pins.
Header J7
1
3
5
7
9
2
4
6
8
10
GND
TDO
TDI1
TRSTn1
TMS1
TCK1
Note: These signals are pulled up by a 1 k
resistor at the LSI402ZX.
GND
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