參數(shù)資料
型號(hào)： E28F200B5B60
廠商： INTEL CORP
元件分類： PROM
英文描述： DIRECTIONAL COUPLER, 20DB, SMT
中文描述： 256K X 8 FLASH 5V PROM, 70 ns, PDSO48
封裝： 12 X 20 MM, TSOP-48
文件頁(yè)數(shù)： 28/44頁(yè)
文件大小： 345K
代理商： E28F200B5B60
28F200B5, 28F004/400B5, 28F800B5
E
34
PRELIMINARY
5.6
AC Characteristics—Read Operations—Commercial and Extended
Temperature
Temp
Commercial
Extended
Speed
-60/-70
-80/-90
#
Sym
Parameter
VCC
5V
± 5%(4) 5V±10% (5) 5V± 10%(5) 5V± 10%(5) Unit
Load
30 pF
100 pF
Notes
Min
Max
Min
Max
Min
Max
Min
Max
R1
tAVAV
Read Cycle
2, 4 Mbit
7
55
70
80
ns
Time
8 Mbit
70
80
90
ns
R2
tAVQV
Address to
2, 4 Mbit
7
55
70
80
ns
Output Delay
8 Mbit
70
80
90
ns
R3
tELQV
CE# to
2, 4 Mbit
2,7
55
70
80
ns
Output Delay
8 Mbit
70
80
90
ns
R4
tGLQV
OE# to Output Delay
2
30
35
40
ns
R5
tPHQV RP# to Output Delay
450
ns
R6
tELQX
CE# to Output in Low Z
3
0
ns
R7
tGLQX
OE# to Output in Low Z
3
0
ns
R8
tEHQZ
CE# to Output in High Z
3
20
25
ns
R9
tGHQZ OE# to Output in High Z
3
20
25
ns
R10
tOH
Output Hold from Address,
CE#, or OE# Change,
Whichever Occurs First
30
0
ns
NOTES:
1.
See AC Input/Output Reference Waveform for timing measurements.
2.
OE# may be delayed up to tCE–tOE after the falling edge of CE# without impact on tCE.
3.
Sampled, but not 100% tested.
4.
See
Test Configuration (Figure 13), 5 V High-Speed Test component values.
5.
See
Test Configuration (Figure 13), 5 V Standard Test component values.
6.
Dynamic BYTE# switching between word and byte modes is not supported. Mode changes must be made when the device
is in deep power-down or powered down.
7.
As of the publication date of this document, not all 28F200B5 –60 devices meet the 55 ns read specification. Please refer
to the
5 Volt Boot Block Flash Memory Family 28F200B5, 28F004/400B5, 28F800B5 Specification Updateto determine
the specific 28F200B5 –T/B60 material that is capable of 55 ns read access times. All other 28F200B5 T/B60 devices are
capable of 60 ns read access times when VCC = 5 V ± 5% and 30 pF load.
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