參數(shù)資料
型號: AT75C1010
英文描述: AT75C1010 Telephony Software Module [Updated 11/01. 29 Pages] This software module runs on the OakDSPCore subsystem of the AT75 series SIAP. expanding its capabilities and making the processor flexible and east to integrate into most operating systems.
中文描述: AT75C1010電話軟件模塊[更新11/01。 29頁]本軟件模塊上運行的AT75系列OakDSPCore子系統(tǒng)統(tǒng)計所。擴大其能力,使處理器的靈活和東部地區(qū)融入大多數(shù)操作系統(tǒng)。
文件頁數(shù): 73/171頁
文件大小: 1288K
代理商: AT75C1010
164
AT75C DSP Subsystem
1368C–INTAP–08/02
Figure 15. Connection of a Codec Device in Slave Mode
Note that programming SCLK and FS in opposite directions is not recommended.
Serial Clock
Configuration
The direction of the serial clock SCLK is controlled by the SCIO bit in CODCNT. When
SCIO is low, the codec interface is said to be in master mode; when SCIO is high, the
codec interface is said to be in slave mode.
Serial Clock in Master Mode
When SCIO is low, the SCLK pin is an input of the AT75C.
The SCLK signal is internally clocked and the resynchronized signal is used as the shift
clock for the transmit and receive shift registers. When SCIO is low, the internal SCLK
generator is disabled and the field SD[7:0] in CODSCK is not used.
The active edge of the serial clock can be programmed independently for the transmitter
and the receiver. When the TES bit in CODSCK is low, the transmitted bits are shifted
out on the rising edge of XSCLK. When TES is high, the transmitted bits are shifted out
on the falling edge of XSCLK.
When the RES bit in CODSCK is low, the received bits are latched on the falling edge of
XSCLK.
Serial Clock in Slave Mode
When SCIO is high, the SCLK pin is an output of the AT75C. An internal clock generator
is used to produce the SCLK signal.
The active edge of SCLK can be programmed independently for the transmitter and the
receiver. When the TES bit in CODSCK is low, the transmitted bits are shifted out on the
rising edge of SCLK. When TES is high, the transmitted bits are shifted out on the falling
edge of SCLK.
When the RES bit in CODSCK is low, the received bits are latched on the falling edge of
SCLK.
The generated SCLK signal is a 50% duty cycle clock whose frequency is controlled by
the SD[7:0] field in CODSCK. The SCLK is derived from the DSP subsystem clock
((Quartz Clock) x 2.5 for AT75C310, (Quartz Clock) x 3.75 for AT75C220) by a program-
mable counter. The count value is stored in SD[7:0].
Codec Device
AT75C
SDO
SDI
SCLK
FS
SDI
SDO
Clocks
Generator
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