參數(shù)資料
型號(hào): AT75C1010
英文描述: AT75C1010 Telephony Software Module [Updated 11/01. 29 Pages] This software module runs on the OakDSPCore subsystem of the AT75 series SIAP. expanding its capabilities and making the processor flexible and east to integrate into most operating systems.
中文描述: AT75C1010電話(huà)軟件模塊[更新11/01。 29頁(yè)]本軟件模塊上運(yùn)行的AT75系列OakDSPCore子系統(tǒng)統(tǒng)計(jì)所。擴(kuò)大其能力,使處理器的靈活和東部地區(qū)融入大多數(shù)操作系統(tǒng)。
文件頁(yè)數(shù): 90/171頁(yè)
文件大小: 1288K
代理商: AT75C1010
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25
AT75C DSP Subsystem
1368C–INTAP–08/02
Status Register 1
PS: Product Shifter Control
The product shifter control bits control the scaling shifter at the output of register P as follows:
The PS bits are cleared during processor reset.
The PS bits can be modified by writing to ST1.
PAGE: Data Memory Space Page
Used for direct address. Refer to “Memory Addressing Modes” on page 21.
The PAGE bits can be modified by the LOAD instruction, the LPG instruction or by writing to ST1.
Status Register 2
IP1, IP0, IP2: Interrupt Pending
IP0 – Interrupt pending for INT0
IP1 – Interrupt pending for INT1
IP2 – Interrupt pending for INT2
The interrupt pending bit is set when the corresponding interrupt is active. The bit reflects the interrupt level regardless of
the mask bits.
The IPx bits are read-only.
IU1, IU0: IUSER0, IUSER1
The IUSERx bits reflect the logic state of the corresponding user input pins.
The IUSERx bits are read-only bits.
OU1, OU0: OUSER0, OUSER1
The OUSERx bits define the logic state of the corresponding user output pins.
The OUSERx bits are cleared during processor reset.
The OUSERx bits can be modified by writing to ST2.
S: Shift Mode
The shift mode bit defines the shift method. Affects all shift instructions: SHFC, SHFI, MODA, MODB, MOVS and MOVSI.
15
14
13
12
11
10
9
8
A1E
PS
––
76
54
32
10
PAGE
PS Bit
Number of Shifts
Bit 11
Bit 10
00
No shift
0
1
Shift right by one
1
0
Shift left by one
1
Shift left by two
15
14
13
12
11
10
9
8
IP1
IP0
IP2
---
IU1
IU0
OU1
OU0
76
54
32
10
S
IM2
M5
M4
M3
M2
M1
M0
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