參數(shù)資料
型號: AT75C1010
英文描述: AT75C1010 Telephony Software Module [Updated 11/01. 29 Pages] This software module runs on the OakDSPCore subsystem of the AT75 series SIAP. expanding its capabilities and making the processor flexible and east to integrate into most operating systems.
中文描述: AT75C1010電話軟件模塊[更新11/01。 29頁]本軟件模塊上運行的AT75系列OakDSPCore子系統(tǒng)統(tǒng)計所。擴大其能力,使處理器的靈活和東部地區(qū)融入大多數(shù)操作系統(tǒng)。
文件頁數(shù): 82/171頁
文件大小: 1288K
代理商: AT75C1010
18
AT75C DSP Subsystem
1368C–INTAP–08/02
Repeat and Block-repeat
Unit
The Repeat/Block-repeat unit performs the hardware-loop calculations and controls
execution without overhead (other than the one-time execution of set up instructions
REP or BKREP for initialization of repeat or block-repeat mechanism, respectively).
Four nested levels of block-repeat can be performed and the REP instruction can be
performed inside each one of the these levels.
The number of repetitions can be a fixed value embedded in the instruction code or a
value transferred from one of the processor’s 16-bit registers. This option supports cal-
culating the number of repetitions in run-time.
For the repeat operation, the unit contains an internal 16-bit repeat counter (REPC) for
repeating a single-word instruction from 1 to 65536 repetitions. REPC counter is read-
able by the programmer.
In block-repeat operation, the last and first addresses of a loop are stored in 16-bit dedi-
cated registers. A 16-bit dedicated counter, LC, counts the number of loop repetitions (1
- 65536). In case of nested block-repeats, it saves these values in internal registers. The
LC of each level can be accessed by the user; the start-address and end-address regis-
ters and the internal shadow registers cannot be accessed as registers by the
programmer. An indication of the block-repeat nesting level is a read-only block-repeat
nesting counter (BC2, BC1, BC0) in the internal configuration register (ICR). See also
“Internal Configuration Register” on page 29. The 16-bit block-repeat loop counter (LC)
is one of the global registers. The LC register can be used as an index inside the block-
repeat loop or for determining the value of the block-repeat counter when a jump out of
the block-repeat loop occurs.
The single instruction repeat can reside in each of the block-repeat levels. Both the
repeat and the block-repeat mechanisms are interruptible. For details, on specific limita-
tions, refer to REP and BKREP instructions in “Instruction Set” on page 31.
A BREAK instruction can be used for stopping each of the four nested levels of a block-
repeat. Refer to the BREAK instruction in “Instruction Set” on page 31.
The in-loop (LP) bit in the ICR is set when a block-repeat is executed and reset upon
normal completion of the outer block-repeat loop. When the user resets this bit, it stops
the execution of all four levels of block-repeat. For more details on the LP bit, refer to
“Internal Configuration Register” on page 29. If the LP bit is cleared in the current block-
repeat loop, the processor is no longer in any of the block loop levels (BC2, BC1, BC0
bits in ICR register are cleared). Therefore, when the last address is reached there are
no jumps to the first address of the loop, the counter is not decremented and the proces-
sor continues to the sequential instruction. An exception is when LP is cleared at one of
the last three addresses of the block-repeat. In these cases the effect of clearing LP
takes place only in the next loop. An instruction that reads ICR and starts at last address
of the outer block-repeat loop results in the LP bit equal to zero when the last repetition
of this outer loop is reached.
The LC register may also serve as a 16-bit general-purpose register for temporary
storage.
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