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參數(shù)資料
| 型號： | AT75C1010 |
| 英文描述： | AT75C1010 Telephony Software Module [Updated 11/01. 29 Pages] This software module runs on the OakDSPCore subsystem of the AT75 series SIAP. expanding its capabilities and making the processor flexible and east to integrate into most operating systems. |
| 中文描述： | AT75C1010電話軟件模塊[更新11/01。 29頁]本軟件模塊上運行的AT75系列OakDSPCore子系統(tǒng)統(tǒng)計所。擴大其能力，使處理器的靈活和東部地區(qū)融入大多數(shù)操作系統(tǒng)。 |
| 文件頁數(shù)： | 69/171頁 |
| 文件大?。?/td> | 1288K |
| 代理商： | AT75C1010 |
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160
AT75C DSP Subsystem
1368C–INTAP–08/02
CODFRM (0xEC02)
FD[7:0]
Frame divisor. This 8-bit number is the value by which to divide the serial clock SCLK to derive the frame sync signal FS.
DD[7:0]
Serial data delay. This is the number of SCLK cycles by which to delay the start of the first data bit from FS.
CODSCK (0xEC04)
SD[7:0]
Serial clock divisor. Value by which to divide the system clock to derive the SCLK output in slave mode:
In master mode, this value is not significant.
TES
Transmitter active edge of SCLK. When high, the data on SDO is shifted out on the falling edge of SCLK. When low, the
data on SDO is shifted out on the rising edge of SCLK.
RES
Receiver active edge of SCLK. When high, the data on SDI is sampled on the rising edge of SCLK. When low, the data on
SDI is sampled on the falling edge of SCLK.
FRL
Frame sync length. When high, the generated frame sync lasts one SCLK cycle. When low, the generated frame sync has
a 50% duty cycle.
DWS
Serial data word width select. When high, the transmit and receive shift registers are 32 bits wide. When low, the shift reg-
isters are 16 bits wide.
WT[1:0]
Word type.
00: Single data mode. Each sample represents a sample value.
01: 1 control, 1 data
10: 1 control, 2 data
11: Stereo mode. Two data are transmitted in one sample period, the left data and the right data. The left and right are
discriminated by the polarity of FS.
FPS[1:0]
Frames per sample. This value indicates the expected number of serial data words to be transmitted and received during
one sample period. This value defines the level reached with receive FIFO before the sample ready interrupt is signalled.
15
14
13
12
11
10
9
8
DD[7:0]
76
54
32
10
FD[7:0]
15
14
13
12
11
10
9
8
FPS[1:0]
WT[1:0]
DWS
FRL
RES
TES
76
54
32
10
SD[7:0]
DSP System Clock
AT75C310
(Quartz Clock) x 2.5
AT75C220
(Quartz Clock) x 3.75
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