參數(shù)資料
型號: AT75C1010
英文描述: AT75C1010 Telephony Software Module [Updated 11/01. 29 Pages] This software module runs on the OakDSPCore subsystem of the AT75 series SIAP. expanding its capabilities and making the processor flexible and east to integrate into most operating systems.
中文描述: AT75C1010電話軟件模塊[更新11/01。 29頁]本軟件模塊上運(yùn)行的AT75系列OakDSPCore子系統(tǒng)統(tǒng)計(jì)所。擴(kuò)大其能力,使處理器的靈活和東部地區(qū)融入大多數(shù)操作系統(tǒng)。
文件頁數(shù): 53/171頁
文件大?。?/td> 1288K
代理商: AT75C1010
146
AT75C DSP Subsystem
1368C–INTAP–08/02
Break-on-branch
Operation
The OCEM allows the user to trigger the BI mechanism upon pipe-break events such as
branch, call, interrupt or looping. The user can choose which event of the following list
would cause a breakpoint:
BR, BRR, CALL, CALLR, CALLA, RET, RETI, RETD, RETID, RETS, MOV to PC
Interrupt service start (excluding TRAP)
Transition from the last back to the first address within a block-repeat loop
Program Flow Trace
Buffer
The OCEM contains a 16-stage program flow trace buffer. The buffer dynamically keeps
non-linear program addresses. This means only those program addresses that contain
an instruction that causes a discontinuity in the program flow. The whole program flow
graph can be reconstructed by taking those non-linear addresses and filling in the gaps
using the object code.
The advantage of using the “condensed” trace buffer resides in the number of
addresses that can effectively be kept in the buffer.
The method behind the condensed trace buffer is composed of four principles:
1.
Only branches that have effectively been taken are recorded. For example, a
conditional branch not causing code discontinuity due to a false condition will not
be recorded.
2.
If the non-sequential instruction has a destination address explicitly coded in the
program (e.g., BR, BRR, CALL, CALLR), only the instruction address is
recorded.
3.
If the non-sequential instruction has a destination address not explicitly coded in
the program (e.g., CALLA, RET or MOV to PC), the instruction address as well
as the target address is recorded.
4.
Interrupts are treated as non-sequential instructions. However, they can arrive
anywhere and, although the target destination is known, the source (the last
instruction address being executed prior to the branch to the interrupt vector)
cannot be derived easily. Therefore, for the interrupt case, the source address
(i.e., the last instruction address before servicing the interrupt) as well as the
destination address (the vector address) is recorded in the trace buffer.
There is an option for trace buffer full breakpoint by setting the bit TBF in the MODE reg-
ister. The bit TBF indicates the cause of the breakpoint. If the TBF bit is disabled, the
trace buffer would contain the last 16 non-sequential recordings. Once the whole buffer
is read, it is filled with all 1s.
The trace memory mechanism contains one extra bit per trace stage that is used to tag
two-word instructions.
Note that:
“Non-sequential” addresses within the breakpoint handler are not recorded.
The PROM address in MOVP instruction and the PRAM address in MOVD
instruction are not recorded.
Non-sequential fetches that are due to TRAP instruction (as well as TRAP/BI
breakpoint) are not recorded.
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