參數(shù)資料
型號(hào)： DSPIC30F6010-20E/PF
廠商： Microchip Technology
文件頁(yè)數(shù)： 88/110頁(yè)
文件大?。?/td> 0K
描述： IC DSPIC MCU/DSP 144K 80TQFP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 90
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 20 MIPS
連通性： CAN，I²C，SPI，UART/USART
外圍設(shè)備： 高級(jí)欠壓探測(cè)/復(fù)位，LVD，電機(jī)控制 PWM，QEI，POR，PWM，WDT
輸入/輸出數(shù)： 68
程序存儲(chǔ)器容量： 144KB（48K x 24）
程序存儲(chǔ)器類(lèi)型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 80-TQFP
包裝： 托盤(pán)
配用： DM300019-ND - BOARD DEMO DSPICDEM 80L STARTER
AC164314-ND - MODULE SKT FOR PM3 80PF
DM300020-ND - BOARD DEV DSPICDEM MC1 MOTORCTRL
其它名稱： DSPIC30F601020EPF
2006 Microchip Technology Inc.
DS70119E-page 77
dsPIC30F6010
13.4.2
PWM PERIOD
The PWM period is specified by writing to the PRx reg-
ister. The PWM period can be calculated using
EQUATION 13-1:
PWM PERIOD
PWM frequency is defined as 1/[PWM period].
When the selected TMRx is equal to its respective
period register, PRx, the following four events occur on
the next increment cycle:
TMRx is cleared.
The OCx pin is set.
- Exception 1: If PWM duty cycle is 0x0000,
the OCx pin will remain low.
- Exception 2: If duty cycle is greater than PRx,
the pin will remain high.
The PWM duty cycle is latched from OCxRS into
OCxR.
The corresponding timer interrupt flag is set.
See Figure 13-1 for key PWM period comparisons.
Timer3 is referred to in the figure for clarity.
FIGURE 13-1:
PWM OUTPUT TIMING
13.5
Output Compare Operation During
CPU Sleep Mode
When the CPU enters the Sleep mode, all internal
clocks are stopped. Therefore, when the CPU enters
the Sleep state, the output compare channel will drive
the pin to the active state that was observed prior to
entering the CPU Sleep state.
For example, if the pin was high when the CPU
entered the Sleep state, the pin will remain high. Like-
wise, if the pin was low when the CPU entered the
Sleep state, the pin will remain low. In either case, the
output compare module will resume operation when
the device wakes up.
13.6
Output Compare Operation During
CPU Idle Mode
When the CPU enters the Idle mode, the output
compare module can operate with full functionality.
The output compare channel will operate during the
CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at
logic 0 and the selected time base (Timer2 or Timer3)
is enabled and the TSIDL bit of the selected timer is
set to logic 0.
13.7
Output Compare Interrupts
The output compare channels have the ability to gener-
ate an interrupt on a compare match, for whichever
match mode has been selected.
For all modes except the PWM mode, when a compare
event occurs, the respective interrupt flag (OCxIF) is
asserted and an interrupt will be generated, if enabled.
The OCxIF bit is located in the corresponding IFS
Status register, and must be cleared in software. The
interrupt is enabled via the respective compare inter-
rupt enable (OCxIE) bit, located in the corresponding
IEC Control register.
For the PWM mode, when an event occurs, the respec-
tive timer interrupt flag (T2IF or T3IF) is asserted and
an interrupt will be generated, if enabled. The IF bit is
located in the IFS0 Status register, and must be cleared
in software. The interrupt is enabled via the respective
Timer Interrupt Enable bit (T2IE or T3IE), located in the
IEC0 Control register. The output compare interrupt
flag is never set during the PWM mode of operation.
PWM period = [(PRx) + 1] 4 TOSC
(TMRx prescale value)
Period
Duty Cycle
TMR3 = Duty Cycle (OCxR)
TMR3 = PR3
T3IF = 1
(Interrupt Flag)
OCxR = OCxRS
TMR3 = PR3
(Interrupt Flag)
OCxR = OCxRS
T3IF = 1
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