參數(shù)資料
型號: DSPIC30F6010-20E/PF
廠商: Microchip Technology
文件頁數(shù): 106/110頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 144K 80TQFP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
標準包裝: 90
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 20 MIPS
連通性: CAN,I²C,SPI,UART/USART
外圍設(shè)備: 高級欠壓探測/復(fù)位,LVD,電機控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 68
程序存儲器容量: 144KB(48K x 24)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 80-TQFP
包裝: 托盤
配用: DM300019-ND - BOARD DEMO DSPICDEM 80L STARTER
AC164314-ND - MODULE SKT FOR PM3 80PF
DM300020-ND - BOARD DEV DSPICDEM MC1 MOTORCTRL
其它名稱: DSPIC30F601020EPF
2006 Microchip Technology Inc.
DS70119E-page 93
dsPIC30F6010
15.13 PWM Update Lockout
For a complex PWM application, the user may need to
write up to four duty cycle registers and the time base
period register, PTPER, at a given time. In some appli-
cations, it is important that all buffer registers be written
before the new duty cycle and period values are loaded
for use by the module.
The PWM update lockout feature is enabled by setting
the UDIS control bit in the PWMCON2 SFR. The UDIS
bit affects all duty cycle buffer registers and the PWM
time base period buffer, PTPER. No duty cycle
changes or period value changes will have effect while
UDIS = 1.
15.14 PWM Special Event Trigger
The PWM module has a special event trigger that
allows A/D conversions to be synchronized to the PWM
time base. The A/D sampling and conversion time may
be programmed to occur at any point within the PWM
period. The special event trigger allows the user to min-
imize the delay between the time when A/D conversion
results are acquired and the time when the duty cycle
value is updated.
The PWM special event trigger has an SFR named
SEVTCMP, and five control bits to control its operation.
The PTMR value for which a special event trigger
should occur is loaded into the SEVTCMP register.
When the PWM time base is in an Up/Down Counting
mode, an additional control bit is required to specify the
counting phase for the special event trigger. The count
phase is selected using the SEVTDIR control bit in the
SEVTCMP SFR. If the SEVTDIR bit is cleared, the spe-
cial event trigger will occur on the upward counting
cycle of the PWM time base. If the SEVTDIR bit is set,
the special event trigger will occur on the downward
count cycle of the PWM time base. The SEVTDIR
control bit has no effect unless the PWM time base is
configured for an Up/Down Counting mode.
15.14.1
SPECIAL EVENT TRIGGER
POSTSCALER
The PWM special event trigger has a postscaler that
allows a 1:1 to 1:16 postscale ratio. The postscaler is
configured by writing the SEVOPS<3:0> control bits in
the PWMCON2 SFR.
The special event output postscaler is cleared on the
following events:
Any write to the SEVTCMP register
Any device Reset
15.15 PWM Operation During CPU Sleep
Mode
The Fault A and Fault B input pins have the ability to
wake the CPU from Sleep mode. The PWM module
generates an interrupt if either of the Fault pins is
driven low while in Sleep.
15.16 PWM Operation During CPU Idle
Mode
The PTCON SFR contains a PTSIDL control bit. This
bit determines if the PWM module will continue to
operate or stop when the device enters Idle mode. If
PTSIDL = 0, the module will continue to operate. If
PTSIDL = 1, the module will stop operation as long as
the CPU remains in Idle mode.
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