- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377002 > DSPE56007FJ88 DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC PDF資料下載
參數(shù)資料
| 型號： | DSPE56007FJ88 |
| 英文描述： | DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC |
| 中文描述： | 數(shù)字信號處理器| 24位|的CMOS | QFP封裝| 80腳|塑料 |
| 文件頁數(shù)： | 15/83頁 |
| 文件大小： | 382K |
| 代理商： | DSPE56007FJ88 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁
Signal/Connection Descriptions
Interrupt and Mode Control
MOTOROLA
DSP56007/D
1-9
MODC
NMI
Input,
edge-
triggered
Input (MODC)
Mode Select C
—This input signal has two functions:
to work with the MODA and MODB signals to select
the DSP’s initial operating mode, and
to allow an external device to request a DSP
interrupt after internal synchronization.
MODC is read and internally latched in the DSP when the
processor exits the Reset state. The logic state present on the
MODA, MODB, and MODC pins selects the initial DSP
operating mode. Several clock cycles after leaving the Reset
state, the MODC signal changes to the Non-Maskable
Interrupt request, NMI. The DSP operating mode can be
changed by software after reset.
Non-Maskable Interrupt Request
—The NMI input is a
negative-edge-triggered external interrupt request. This is a
level 3 interrupt that can not be masked out. Triggering
occurs at a voltage level and is not directly related to the fall
time of the interrupt signal. However, as the fall time of the
interrupt signal increases, the probability that noise on NMI
will generate multiple interrupts also increases. Hardware
reset causes this input to function as MODC.
RESET
input
active
RESET
—This input causes a direct hardware reset of the
processor. When RESET is asserted, the DSP is initialized and
placed in the Reset state. A Schmitt-trigger input is used for
noise immunity. When the reset signal is deasserted, the initial
DSP operating mode is latched from the MODA, MODB, and
MODC signals. The DSP also samples the PINIT signal and
writes its status into the PEN bit of the PLL Control Register.
When the DSP comes out of the Reset state, deassertion
occurs at a voltage level and is not directly related to the rise
time of the RESET signal. However, the probability that
noise on RESET will generate multiple resets increases with
increasing rise time of the RESET signal.
For proper hardware reset to occur, the clock must be active,
since a number of clock ticks are required for proper
propagation of the hardware Reset state.
Table 1-7
Interrupt and Mode Control Signals (Continued)
Signal Name
Signal
Type
State during
Reset
Signal Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSPCOMMANDUM | Universal Command Converter for DSP User＇s Manual |
| DSPCOMMPARALLELUM | Parallel Port Command Converter for DSP User＇s Manual |
| DSPCOMMPCIUM | PCI Command Converter for DSP User＇s Manual |
| DSPG4001-71 | Telecommunication IC |
| DSPG5002 | Analog IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSPF3-S7-120V | 制造商:Black Box Corporation 功能描述:DIGITAL SIGNAGE POWER FILTER |
| DSPF3-S7-120V-W1 | 制造商:Black Box Corporation 功能描述:1 YEAR WARRANTY FOR DSPF3-S7-120V |
| DSPF3-S7-120V-W3 | 制造商:Black Box Corporation 功能描述:3 YEAR WARRANTY FOR DSPF3-S7-120V |
| DSPF56362PV100 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| DSPFPK52 | 制造商:BARRY CONTROLS/VLIER 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。