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| 型號(hào)： | DSPB56364AF100 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 67/148頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT AUD 100MHZ 100-LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | DSP56K/Symphony |
| 類型： | 音頻處理器 |
| 接口： | 主機(jī)接口，I²C，SAI，SPI |
| 時(shí)鐘速率： | 100MHz |
| 非易失內(nèi)存： | ROM（24 kB） |
| 芯片上RAM： | 11.25kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
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Reset, Stop, Mode Select, and Interrupt Timing
DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor
3-9
29
Delay from
IRQA, IRQB, IRQD, NMI assertion to external
memory (DMA source) access address out valid
4.25
× T
C + 2.0
44.0
—
ns
1 V
CC = 3.3 V ± 0.16 V; TJ = 0°C to + 105°C, CL = 50 pF
2 Use expression to compute maximum value.
3 Periodically sampled and not 100% tested
4 For an external clock generator, RESET duration is measured during the time in which RESET is asserted, V
CC is valid, and
the EXTAL input is active and valid.
For internal oscillator, RESET duration is measured during the time in which RESET is asserted and VCC is valid. The specified
timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the
crystal and other components connected to the oscillator and reflects worst case conditions.
When the VCC is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the
device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should
minimize this state to the shortest possible duration.
5 For an external clock generator, RESET duration is measured during the time in which RESET is asserted, V
CC is valid, and
the EXTAL input is active and valid.
For internal oscillator, RESET duration is measured during the time in which RESET is asserted and VCC is valid. The specified
timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the
crystal and other components connected to the oscillator and reflects worst case conditions.
When the VCC is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the
device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should
minimize this state to the shortest possible duration.
6 When using fast interrupts and IRQA, IRQB, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent
multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when using
fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
7 WS = number of wait states (measured in clock cycles, number of T
C)
8 This timing depends on several settings:
For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL
Bit 17 = 0), a stabilization delay is required to assure the oscillator is stable before executing programs. In that case, resetting
the Stop delay (OMR Bit 6 = 0) will provide the proper delay. While it is possible to set OMR Bit 6 = 1, it is not recommended
and these specifications do not guarantee timings for that case.
For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no stabilization
delay is required and recovery time will be minimal (OMR Bit 6 setting is ignored).
For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined by
the PCTL Bit 17 and OMR Bit 6 settings.
For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked.
The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in
parallel with the stop delay counter, and stop recovery will end when the last of these two events occurs. The stop delay
counter completes count or PLL lock procedure completion.
PLC value for PLL disable is 0.
The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency (i.e., for 100 MHz it is 4096/100
MHz = 40
μs). During the stabilization period, T
C, TH, and TL will not be constant, and their width may vary, so timing may vary
as well.
9. If PLL does not lose lock.
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1 (continued)
No.
Characteristics
Expression2
Min
Max
Unit
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