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參數(shù)資料
| 型號： | DSPB56364AF100 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 35/148頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT AUD 100MHZ 100-LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | DSP56K/Symphony |
| 類型： | 音頻處理器 |
| 接口： | 主機(jī)接口，I²C，SAI，SPI |
| 時(shí)鐘速率： | 100MHz |
| 非易失內(nèi)存： | ROM（24 kB） |
| 芯片上RAM： | 11.25kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
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Enhanced Serial Audio Interface
DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor
2-9
2.8
Enhanced Serial Audio Interface
Table 2-10 Enhanced Serial Audio Interface Signals
Signal
Name
Signal Type
State During
Reset
Signal Description
HCKR
Input or output
GPIO
disconnected
High Frequency Clock for Receiver—When programmed as an input, this
signal provides a high frequency clock source for the ESAI receiver as an
alternate to the DSP core clock. When programmed as an output, this signal
can serve as a high-frequency sample clock (e.g., for external digital to analog
converters [DACs]) or as an additional system clock.
PC2
Input, output, or
disconnected
GPIO
disconnected
Port C 2—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
HCKT
Input or output
GPIO
disconnected
High Frequency Clock for Transmitter—When programmed as an input, this
signal provides a high frequency clock source for the ESAI transmitter as an
alternate to the DSP core clock. When programmed as an output, this signal
can serve as a high frequency sample clock (e.g., for external DACs) or as an
additional system clock.
PC5
Input, output, or
disconnected
GPIO
disconnected
Port C 5—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
FSR
Input or output
GPIO
disconnected
Frame Sync for Receiver—This is the receiver frame sync input/output signal.
In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync
input or output used by all the enabled receivers. In the synchronous mode
(SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the
transmitter external buffer enable control (TEBE=1, RFSD=1).
When this pin is configured as serial flag pin, its direction is determined by the
RFSD bit in the RCCR register. When configured as the output flag OF1, this
pin will reflect the value of the OF1 bit in the SAICR register, and the data in the
OF1 bit will show up at the pin synchronized to the frame sync in normal mode
or the slot in network mode. When configured as the input flag IF1, the data
value at the pin will be stored in the IF1 bit in the SAISR register, synchronized
by the frame sync in normal mode or the slot in network mode.
PC1
Input, output, or
disconnected
GPIO
disconnected
Port C 1—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
FST
Input or output
GPIO
disconnected
Frame Sync for Transmitter—This is the transmitter frame sync input/output
signal. For synchronous mode, this signal is the frame sync for both transmitters
and receivers. For asynchronous mode, FST is the frame sync for the
transmitters only. The direction is determined by the transmitter frame sync
direction (TFSD) bit in the ESAI transmit clock control register (TCCR).
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