參數(shù)資料
型號: DSPA56721AG
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
中文描述: SymphonyTM DSP56720 / DSP56721多核音頻處理器
文件頁數(shù): 29/54頁
文件大?。?/td> 671K
代理商: DSPA56721AG
Symphony
TM
DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
29
95
HCKR/HCKT clock cycle
2 x T
C
10
ns
96
HCKT input rising edge to SCKT output
18.0
ns
97
HCKR input rising edge to SCKR output
18.0
ns
Notes:
1.
2.
V
CORE_VDD
= 1.00 ± 0.10 V; T
J
= -40°C to 125°C; C
L
= 50 pF.
i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(Asynchronous implies that SCKT and SCKR are two different clocks.)
i ck s = internal clock, synchronous mode
(Synchronous implies that SCKT and SCKR are the same clock.)
bl = bit length
wl = word length
wr = word length relative
SCKT(SCKT pin) = transmit clock
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
For the internal clock, the external clock cycle is defined by Tc and the ESAI control register.
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal
waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit
clock of the first word in frame.
Periodically sampled and not 100% tested.
ESAI_1, ESAI_2, ESAI_3 specs match those of ESAI.
3.
4.
5.
6.
7.
8.
Table 13. Enhanced Serial Audio Interface Timing Parameters (Continued)
No.
Characteristics
1, 3, 4
Symbol
Expression
5
Min
Max
Condition
2
Unit
相關PDF資料
PDF描述
DSPB56720AG SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
DSPB56721AF SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
DSPB56721AG SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
DSP56800ERM 16-bit Digital Signal Controllers
DSP56800E Digitial Signal Controller
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