參數(shù)資料
型號(hào)： DSPA56721AG
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
中文描述： SymphonyTM DSP56720 / DSP56721多核音頻處理器
文件頁數(shù)： 28/54頁
文件大?。?/td> 671K
代理商： DSPA56721AG
Symphony
TM
DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
28
80
SCKT rising edge to FST out (wr) high
6
–
–
–
–
20.0
10.0
x ck
i ck
ns
81
SCKT rising edge to FST out (wr) low
6
–
–
–
–
22.0
12.0
x ck
i ck
ns
82
SCKT rising edge to FST out (wl) high
–
–
–
–
19.0
9.0
x ck
i ck
ns
83
SCKT rising edge to FST out (wl) low
–
–
–
–
20.0
10.0
x ck
i ck
ns
84
SCKT rising edge to data out enable from high
impedance
–
–
–
–
22.0
17.0
x ck
i ck
ns
85
SCKT rising edge to transmitter #0 drive enable
assertion
–
–
–
–
17.0
11.0
x ck
i ck
ns
86
SCKT rising edge to data out valid
–
–
–
–
18.0
13.0
x ck
i ck
ns
87
SCKT rising edge to data out high impedance
7
–
–
–
–
21.0
16.0
x ck
i ck
ns
88
SCKT rising edge to transmitter #0 drive enable
deassertion
7
–
–
–
–
14.0
9.0
x ck
i ck
ns
89
FST input (bl, wr) setup time before SCKT falling edge
6
–
–
2.0
18.0
–
–
x ck
i ck
ns
90
FST input (wl) setup time before SCKT falling edge
–
–
2.0
18.0
–
–
x ck
i ck
ns
91
FST input hold time after SCKT falling edge
–
–
4.0
5.0
–
–
x ck
i ck
ns
92
FST input (wl) to data out enable from high impedance
–
–
–
21.0
–
ns
93
FST input (wl) to transmitter #0 drive enable assertion
–
–
–
14.0
–
ns
94
Flag output valid after SCKT rising edge
–
–
–
–
14.0
9.0
x ck
i ck
ns
Table 13. Enhanced Serial Audio Interface Timing Parameters (Continued)
No.
Characteristics
1, 3, 4
Symbol
Expression
5
Min
Max
Condition
2
Unit
相關(guān)PDF資料
PDF描述
DSPB56720AG SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
DSPB56721AF SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
DSPB56721AG SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
DSP56800ERM 16-bit Digital Signal Controllers
DSP56800E Digitial Signal Controller
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