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參數(shù)資料
| 型號： | DSPA56721AG |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors |
| 中文描述： | SymphonyTM DSP56720 / DSP56721多核音頻處理器 |
| 文件頁數(shù)： | 12/54頁 |
| 文件大小： | 671K |
| 代理商： | DSPA56721AG |
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Symphony
TM
DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
12
2.1.5
AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a V
IL
maximum of 0.8 V and a V
IH
minimum of 2.0 V for all pins. AC timing specifications, which are referenced to a device input signal, are measured in
production with respect to the 50% point of the respective input signal’s transition. DSP56720/DSP56721 output levels are
measured with the production test machine V
OL
and V
OH
reference levels set at 0.4 V and 2.4 V, respectively.
2.1.6
Internal Clocks
Internal clock characteristics are listed in
Table 7
.
Internal supply current
1
(core only) at internal clock of
200 MHz
In Normal mode
I
CCI
–
190
780
mA
In Wait mode
I
CCW
–
90
680
mA
In Stop mode
2
I
CCS
–
50
640
mA
Input capacitance
C
IN
–
–
10
pF
Notes:
1.
The Current Consumption section provides a formula to compute the estimated current requirements in Normal mode. In order
to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive
DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this benchmark. This
reflects typical DSP applications. Typical internal supply current is measured with V
CORE_VDD
= 1.0V, V
DD_IO
= 3.3V at T
J
= 25°C.
Maximum internal supply current is measured with V
CORE_VDD
= 1.10V, V
IO_VDD)
= 3.6V at T
J
= 125°C.
In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to float).
2.
Table 7. Internal Clocks
No.
Characteristics
Symbol
Min
Typ
Max
Unit
Condition
1
Comparison Frequency
Fref
2
–
8
MHz
Fref = Fin/NR
2
Input Clock Frequency
Fin
Max = 200 MHz
3
PLL VCO Frequency
Fvco
200
–
400
MHz
Fvco = (Fin * NF)/NR
4
Output Clock Frequency
[1]
with PLL enabled
with PLL disabled
Fout
25
–
–
200
200
MHz
Fout= Fvco/NO
Fout = Fin
5
Duty Cycle
–
40
50
60
%
Fvco=
200 MHz – 400 MHz
Notes:
Fin = External frequency, NF = Multiplication Factor, NR = Predivision Factor, NO = Output Divider
Table 6. DC Electrical Characteristics (Continued)
Characteristics
Symbol
Min
Typ
Max
Unit
相關(guān)PDF資料 |
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|---|---|
| DSPB56720AG | SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors |
| DSPB56721AF | SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors |
| DSPB56721AG | SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors |
| DSP56800ERM | 16-bit Digital Signal Controllers |
| DSP56800E | Digitial Signal Controller |
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