參數(shù)資料
型號(hào)： DSP56F803E
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù)： 13/52頁(yè)
文件大小： 414K
代理商： DSP56F803E
Pulse Width Modulator (PWM) Signals
56F803 Technical Data, Rev. 15
Freescale Semiconductor
13
2.6 Pulse Width Modulator (PWM) Signals
1
RESET
Input
(Schmitt)
Input
Reset
—This input is a direct hardware reset on the processor.
When RESET is asserted low, the controller is initialized and placed
in the Reset state. A Schmitt trigger input is used for noise immunity.
When the RESET pin is deasserted, the initial chip operating mode
is latched from the EXTBOOT pin. The internal reset signal will be
deasserted synchronous with the internal clocks, after a fixed
number of internal clocks.
To ensure a complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.
1
EXTBOOT
Input
(Schmitt)
Input
External Boot
—This input is tied to V
DD
to force device to boot from
off-chip memory. Otherwise, it is tied to V
SS
.
Table 2-10 Pulse Width Modulator (PWMA) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
6
PWMA0
–
5
Output
Tri-stated
PWMA0
–
5
— These are six PWMA output pins.
3
ISA0
–
2
Input
(Schmitt)
Input
ISA0
–
2
— These three input current status pins are used for
top/bottom pulse width correction in complementary channel
operation for PWMA.
3
FAULTA0
–
2
Input
(Schmitt)
Input
FAULTA0
–
2
— These three fault input pins are used for disabling
selected PWMA outputs in cases where fault conditions originate
off-chip.
Table 2-9 Interrupt and Program Control Signals (Continued)
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
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