參數(shù)資料
型號(hào)： DSP5685xUM
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù)： 35/60頁(yè)
文件大?。?/td> 836K
代理商： DSP5685XUM
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56854 Technical Data, Rev. 6
Freescale Semiconductor
35
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
t
IDM
18T
—
ns
4-14
t
IDM -FAST
14T
—
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
t
IG
18T
—
ns
4-14
t
IG -FAST
14T
—
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State
4
t
IRI
22T
—
ns
4-15
t
IRI -FAST
18T
—
Delay from IRQA Assertion (exiting Stop) to External
Data Memory
5
t
IW
1.5T
—
ns
4-16
Delay from IRQA Assertion (exiting Wait) to External
Data Memory
Fast
6
Normal
7
t
IF
18T
22ET
—
—
ns
ns
4-16
RSTO pulse width
8
normal operation
internal reset mode
t
RSTO
128ET
8ET
—
—
—
—
4-17
1.
2.
3.
clock, t
xtal
, t
extal
or t
osc
.
4.
The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is
not the minimum required so that the IRQA interrupt is accepted.
5.
The interrupt instruction fetch is visible on the pins only in Mode 3.
6.
Fast stop mode:
Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is
requested (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes
one less cycle and t
clk
will continue same value it had before stop mode was entered.
7.
Normal stop mode:
As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master
clock, recovery will take an extra cycle (to restart the clock), and t
clk
will resume at the input clock source rate.
8.
ET = External Clock period, For an external crystal frequency of 8MHz, ET=125 ns.
In the formulas, T = clock cycle. For f
op
= 120MHz operation and f
ipb
= 60MHz, T = 8.33ns.
Parameters listed are guaranteed by design.
At reset, the PLL is disabled and bypassed. The part is then put into Run mode and t
clk
assumes the period of the source
Table 4-7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1, 2
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
=
3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
Characteristic
Symbol
Min
Max
Unit
See Figure
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