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| 型號： | DSP5685xUM |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 16-bit Digital Signal Controllers |
| 中文描述： | 16位數(shù)字信號控制器 |
| 文件頁數(shù)： | 28/60頁 |
| 文件大小： | 836K |
| 代理商： | DSP5685XUM |
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56854 Technical Data, Rev. 6
28
Freescale Semiconductor
4.3 Supply Voltage Sequencing and Separation Cautions
Figure 4-2
shows two situations to avoid in sequencing the V
DD
and V
DDIO,
V
DDA
supplies.
Notes:
1. V
DD
rising before V
DDIO
, V
DDA
2. V
DDIO
, V
DDA
rising much faster than V
DD
Figure 4-2 Supply Voltage Sequencing and Separation Cautions
V
DD
should not be allowed to rise early (1). This is usually avoided by running the regulator for the V
DD
supply (1.8V) from the voltage generated by the 3.3V V
DDIO
supply, see
Figure 4-3
. This keeps V
DD
from
rising faster than V
DDIO
.
V
DD
should not rise so late that a large voltage difference is allowed between the two supplies (2).
Typically this situation is avoided by using external discrete diodes in series between supplies, as shown
in
Figure 4-3
. The series diodes forward bias when the difference between V
DDIO
and V
DD
reaches
approximately 2.1, causing V
DD
to rise as V
DDIO
ramps up. When the V
DD
regulator begins proper
operation, the difference between supplies will typically be 0.8V and conduction through the diode chain
reduces to essentially leakage current. During supply sequencing, the following general relationship
should be adhered to:
V
DDIO
> V
DD
> (V
DDIO
- 2.1V)
In practice, V
DDA
is typically connected directly to V
DDIO
with some filtering.
3.3V
1.8V
Time
0
2
1
Supplies Stable
V
DD
V
DDIO,
V
DDA
D
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