
56854 Technical Data, Rev. 6
Freescale Semiconductor
3
56854 General Description
120 MIPS at 120MHz
16K x 16-bit Program SRAM
16K x 16-bit Data SRAM
1K x 16-bit Boot ROM
Access up to 2M words of program or 8M data memory
Chip Select Logic for glue-less interface to ROM and
SRAM
Six (6) independent channels of DMA
Enhanced Synchronous Serial Interfaces (ESSI)
Two (2) Serial Communication Interfaces (SCI)
Serial Port Interface (SPI)
8-bit Parallel Host Interface
General Purpose 16-bit Quad Timer
JTAG/Enhanced On-Chip Emulation (OnCE) for
unobtrusive, real-time debugging
Computer Operating Properly (COP)/Watchdog Timer
Time-of-Day (TOD)
128 LQFP package
Up to 41 GPIO
56854 Block Diagram
JTAG/
Enhanced
OnCE
Program Controller
and
Hardware Looping Unit
Data ALU
16 x 16 + 36
→
36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Address
Generation Unit
Bit
Manipulation
Unit
16-Bit
DSP56800E Core
XTAL
EXTAL
Interrupt
Controller
Quad
Timer
or
GPIOG
4
CLKO
External Address
Bus Switch
External Bus
Interface Unit
4
RESET
IRQA
IRQB
V
DD
V
SSIO
V
DDA
V
SSA
External Data
Bus Switch
Bus Control
WR Enable
CS0-CS3[3:0] or
GPIOA0-GPIOA3[3:0]
RD Enable
A0-20 [20:0]
MODEA-C or
(GPIOH0-H2)
D0-D15 [15:0]
6
Program Memory
16,384 x 16 SRAM
Boot ROM
1024 x 16 ROM
Data Memory
16,384 x 16 SRAM
PDB
PDB
CDBR
CDBW
XAB1
XAB2
XDB2
SPI
or
GPIOF
2 SCI
or
GPIOE
IPBus Bridge (IPBB)
3
6
10
V
DDIO
11
Decoding
Peripherals
4
System
Bus
Control
Memory
PAB
PAB
CDBR
CDBW
V
SS
6
6
ESSI0
or
GPIOC
Host
Interface
or
GPIOB
16
RSTO
DMA
6 channel
POR
Integration
Module
System
COP/
Watch-
dog
Time
of
Day
Clock
Generator
OSC PLL
IPBus CLK
COP/TOD CLK
C
I
I
I
D