參數(shù)資料
型號(hào)： DSP5685xUM
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁數(shù)： 26/60頁
文件大?。?/td> 836K
代理商： DSP5685XUM
56854 Technical Data, Rev. 6
26
Freescale Semiconductor
V
DD
supply current (Core logic, memories, peripherals)
Run
1
Deep Stop
2
Light Stop
3
I
DD4
—
—
—
70
0.05
5
110
10
14
mA
mA
mA
V
DDIO
supply current (I/O circuity)
Run
5
Deep Stop
2
I
DDIO
—
40
0
50
1.5
mA
mA
V
DDA
supply current (analog circuity)
Deep Stop
2
I
DDA
—
60
120
μ
A
Low Voltage Interrupt
6
V
EI
—
2.5
2.85
V
Low Voltage Interrupt Recovery Hysteresis
V
EIH
—
50
—
mV
Power on Reset
7
POR
—
1.5
2.0
V
Note:
no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. PLL set to 240MHz out.
Run (operating) I
DD
measured using external square wave clock source (f
osc
= 4MHz) into XTAL. All inputs 0.2V from rail;
1.
2.
3.
4.
5.
6.
7.
for as long as the internal 2.5V is below 1.8V no matter how long the ramp up rate is. The internally regulated voltage is typically
100 mV less than V
DD
during ramp up until 2.5V is reached, at which time it self-regulates.
Running Core, performing 50% NOP and 50% FIR. Clock at 120 MHz.
Deep Stop Mode - Operation frequency = 4 MHz, PLL set to 4 MHz, crystal oscillator and time of day module operating.
Light Stop Mode - Operation frequency = 120 MHz, PLL set to 240 MHz, crystal oscillator and time of day module operating.
I
DD
includes current for core logic, internal memories, and all internal peripheral logic circuitry.
Running core and performing external memory access. Clock at 120 MHz.
When V
DD
drops below V
EI
max value, an interrupt is generated.
Power-on reset occurs whenever the digital supply drops below 1.8V. While power is ramping up, this signal remains active
Table 4-4 DC Electrical Characteristics (Continued)
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
=
3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
≤
50pF, f
op
= 120MHz
Characteristic
Symbol
Min
Typ
Max
Unit
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