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參數(shù)資料
| 型號： | DSP5685xUM |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | 16-bit Digital Signal Controllers |
| 中文描述： | 16位數(shù)字信號控制器 |
| 文件頁數(shù)： | 20/60頁 |
| 文件大?。?/td> | 836K |
| 代理商： | DSP5685XUM |
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56854 Technical Data, Rev. 6
20
Freescale Semiconductor
121
SC02
GPIOC5
Input
/Output
Input /Output
ESSI Serial Control Pin 2 (SC02)
—This pin is used for frame sync
I/O. SC02 is the frame sync for both the transmitter and receiver in
synchronous mode and for the transmitter only in asynchronous
mode. When configured as an output, this pin is the internally
generated frame sync signal. When configured as an input, this pin
receives an external frame sync signal for the transmitter (and the
receiver in synchronous operation).
Port C GPIO (5)
—This pin is a General Purpose I/O (GPIO) pin
when the ESSI is not in use.
1
MISO
GPIOF0
Input
/Output
Input/Output
SPI Master In/Slave Out (MISO)
—This serial data pin is an input to
a master device and an output from a slave device. The MISO line
of a slave device is placed in the high-impedance state if the slave
device is not selected. The driver on this pin can be configured as
an open-drain driver by the SPI’s Wired-OR mode (WOM) bit when
this pin is configured for SPI operation.
Port F GPIO (0)
—This pin is a General Purpose I/O (GPIO) pin that
can be individually programmed as input or output pin.
2
MOSI
GPIOF1
Input
/Output (Z)
Input/Output
SPI Master Out/Slave In (MOSI)
—This serial data pin is an output
from a master device and an input to a slave device. The master
device places data on the MOSI line a half-cycle before the clock
edge that the slave device uses to latch the data. The driver on this
pin can be configured as an open-drain driver by the SPI’s WOM bit
when this pin is configured for SPI operation.
Port F GPIO (1)
—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
3
SCK
GPIOF2
Input
/Output
Input/Output
SPI Serial Clock (SCK)
—This bidirectional pin provides a serial bit
rate clock for the SPI. This gated clock signal is an input to a slave
device and is generated as an output by a master device. Slave
devices ignore the SCK signal unless the SS pin is active low. In
both master and slave SPI devices, data is shifted on one edge of
the SCK signal and is sampled on the opposite edge, where data is
stable. The driver on this pin can be configured as an open-drain
driver by the SPI’s WOM bit when this pin is configured for SPI
operation. When using Wired-OR mode, the user must provide an
external pull-up device.
Port F GPIO (2)
—This pin is a General Purpose I/O (GPIO) pin that
can be individually programmed as input or output pin.
Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)
Pin No.
Signal Name
Type
Description
相關PDF資料 |
PDF描述 |
|---|---|
| DSP56854E | 16-bit Digital Signal Controllers |
| DSP56854FG120 | 16-bit Digital Signal Controllers |
| DSP56855BU120 | 16-bit Digital Signal Controllers |
| DSP56855BUE | 16-bit Digital Signal Controllers |
| DSP56855E | 16-bit Digital Signal Controllers |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DSP5685XUMAD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP5685XUMAD Rev 2.0 Addendum |
| DSP56ADC16D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 16-Bit |
| DSP56ADC16L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 16-Bit |
| DSP56ADC16P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 16-Bit |
| DSP56ADC16S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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