參數(shù)資料
型號(hào): DSP56852VFE
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù): 9/48頁(yè)
文件大?。?/td> 731K
代理商: DSP56852VFE
Introduction
56852 Technical Data, Rev. 8
Freescale Semiconductor
9
Part 3 Signals and Package Information
All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are
enabled by default. Exceptions:
1. When a pin has GPIO functionality, the pull-up may be disabled under software control.
2. Mode pins D13, D14 and D15 have no pull-up.
3. TCK has a weak pull-down circuit always active.
4. Bidirectional I/O pullups automatically disable when the output is enabled.
This table is presented consistently with the
Signals Identified by Functional Group
figure.
1.
BOLD
entries in the
Type
column represents the state of the pin just out of reset.
2. Ouput(Z) means an output in a High-Z condition.
Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA
Pin No.
Signal Name
Type
Description
E1
V
DD
V
DD
Logic Power
—These pins provide power to the internal structures of
the chip, and should all be attached to V
DD.
J5
V
DD
E9
V
DD
D1
V
SS
V
SS
Logic Power - GND
—These pins provide grounding for the internal
structures of the chip and should all be attached to V
SS.
J4
V
SS
F9
V
SS
C1
V
DDIO
V
DDIO
I/O Power
—These pins provide power for all I/O and ESD structures of
the chip, and should all be attached to V
DDIO.
H1
V
DDIO
J7
V
DDIO
G9
V
DDIO
B9
V
DDIO
A4
V
DDIO
B1
V
SSIO
V
SSIO
I/O Power - GND
—These pins provide grounding for all I/O and ESD
structures of the chip and should all be attached to V
SS.
G1
V
SSIO
J6
V
SSIO
J9
V
SSIO
C9
V
SSIO
A5
V
SSIO
B5
V
DDA
V
DDA
Analog Power
—These pins supply an analog power source
B6
V
SSA
V
SSA
Analog Ground
—This pin supplies an analog ground.
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