參數(shù)資料
型號: DSP56852VFE
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號控制器
文件頁數(shù): 33/48頁
文件大小: 731K
代理商: DSP56852VFE
Synchronous Serial Interface (SSI) Timing
56852 Technical Data, Rev. 8
Freescale Semiconductor
33
4.10 Synchronous Serial Interface (SSI) Timing
Table 4-11 SSI Master Mode
1
Switching Characteristics
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
< 50pF, f
op
= 120MHz
1.
Master mode is internally generated clocks and frame syncs
Parameter
Symbol
Min
Typ
Max
Units
STCK frequency
fs
15
2
MHz
STCK period
3
t
SCKW
66.7
ns
STCK high time
t
SCKH
33.4
ns
STCK low time
t
SCKL
33.4
ns
Output clock rise/fall time
4
ns
Delay from STCK high to STFS (bl) high - Master
4
t
TFSBHM
-1.0
-0.1
ns
Delay from STCK high to STFS (wl) high - Master
4
t
TFSWHM
-1.0
-0.1
ns
Delay from SRCK high to SRFS (bl) high - Master
4
t
RFSBHM
0.1
1.0
ns
Delay from SRCK high to SRFS (wl) high - Master
4
t
RFSWHM
0.1
1.0
ns
Delay from STCK high to STFS (bl) low - Master
4
t
TFSBLM
-1.0
-0.1
ns
Delay from STCK high to STFS (wl) low - Master
4
t
TFSWLM
-1.0
-0.1
ns
Delay from SRCK high to SRFS (bl) low - Master
4
t
RFSBLM
-0.1
0.1
ns
Delay from SRCK high to SRFS (wl) low - Master
4
t
RFSWLM
-0.1
0.1
ns
STCK high to STXD enable from high impedance - Master
t
TXEM
0
1
ns
STCK high to STXD valid - Master
t
TXVM
0
1
ns
STCK high to STXD not valid - Master
t
TXNVM
-0.1
0
ns
STCK high to STXD high impedance - Master
t
TXHIM
-4
0
ns
SRXD Setup time before SRCK low - Master
t
SM
4
ns
SRXD Hold time after SRCK low - Master
t
HM
4
ns
Synchronous Operation (in addition to standard internal clock parameters)
SRXD Setup time before STCK low - Master
t
TSM
4
SRXD Hold time after STCK low - Master
t
THM
4
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