參數(shù)資料
型號： DSP56303VF100R2
廠商： Freescale Semiconductor
文件頁數(shù)： 87/108頁
文件大小： 0K
描述： IC DSP 24BIT 100MHZ 196-BGA
標(biāo)準(zhǔn)包裝： 750
系列： DSP563xx
類型： 定點
接口： 主機接口，SSI，SCI
時鐘速率： 100MHz
非易失內(nèi)存： ROM（576 B）
芯片上RAM： 24kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 196-LBGA
供應(yīng)商設(shè)備封裝： 196-MAPBGA（15x15）
包裝： 帶卷 (TR)
DSP56303 Technical Data, Rev. 11
1-4
Freescale Semiconductor
Signals/Connections
1.3 Clock
1.4 PLL
1.5 External Memory Expansion Port (Port A)
Note:
When the DSP56303 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-
states the relevant Port A signals: A[0–17], D[0–23], AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS.
1.5.1
External Address Bus
Table 1-4.
Clock Signals
Signal Name
Type
State During
Reset
Signal Description
EXTAL
Input
External Clock/Crystal Input—Interfaces the internal crystal oscillator input
to an external crystal or an external clock.
XTAL
Output
Chip-driven
Crystal Output—Connects the internal crystal oscillator output to an external
crystal. If an external clock is used, leave XTAL unconnected.
Table 1-5.
Phase-Locked Loop Signals
Signal Name
Type
State During
Reset
Signal Description
CLKOUT
Output
Chip-driven
Clock Output—Provides an output clock synchronized to the internal core
clock phase.
If the PLL is enabled and both the multiplication and division factors equal one,
then CLKOUT is also synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.
PCAP
Input
PLL Capacitor—An input connecting an off-chip capacitor to the PLL filter.
Connect one capacitor terminal to PCAP and the other terminal to VCCP.
If the PLL is not used, PCAP can be tied to VCC, GND, or left floating.
PINIT
NMI
Input
PLL Initial—During assertion of RESET, the value of PINIT is written into the
PLL enable (PEN) bit of the PLL control (PCTL) register, determining whether
the PLL is enabled or disabled.
Nonmaskable Interrupt—After RESET deassertion and during normal
instruction processing, this Schmitt-trigger input is the negative-edge-triggered
NMI request internally synchronized to CLKOUT.
Note: PINIT/NMI can tolerate 5 V.
Table 1-6.
External Address Bus Signals
Signal Name
Type
State During
Reset, Stop, or
Wait
Signal Description
A[0–17]
Output
Tri-stated
Address Bus—When the DSP is the bus master, A[0–17] are active-high outputs that
specify the address for external program and data memory accesses. Otherwise, the
signals are tri-stated. To minimize power dissipation, A[0–17] do not change state when
external memory spaces are not being accessed.
相關(guān)PDF資料
PDF描述
RAC06-12DC/W CONV AC/DC 6W +/-12V OUT DL T/H
TAJD686M020RNJ CAP TANT 68UF 20V 20% 2917
TPSD227M004R0100 CAP TANT 220UF 4V 20% 2917
RAC06-12SC/W CONV AC/DC 6W 12V OUT SGL T/H
MAX6658MSA+T IC TEMP SENSOR SMBUS 8-SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56303VL100 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56303VL100B1 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56304GC66 制造商:未知廠家 制造商全稱:未知廠家 功能描述:24-Bit Digital Signal Processor
DSP56304GC80 制造商:未知廠家 制造商全稱:未知廠家 功能描述:24-Bit Digital Signal Processor
DSP56304PV66 制造商:未知廠家 制造商全稱:未知廠家 功能描述:24-Bit Digital Signal Processor
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*